CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 93108817, filed on Mar. 31, 2005. All disclosure of the Taiwan application is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to a method of generating absolute time in pregroove (ATIP) data, and more particularly to a method of generating ATIP data based on an original ATIP data signal generated by a wobble signal and an ATIP clock signal.
2. Description of Related Art
During the manufacture of the re-writable compact disk (CD), a shallow groove will be made from the center of the CD toward the outer circumference in spiral way. This groove is so-called pregroove. This pregroove is not a perfect spiral but a little wobbling. Generally, in a CD made by die-casting, each sector includes the timing-related data to control the spin speed of the CD-ROM drive in order to accurately read the data on the CD. A CD-RW drive must have some ways to introduce the laser for recording the data toward the outer circumference in proper sequence and to control the spin speed. That is what the wobbling pregroove is for—to provide the tracking and timing data, which are so-called ATIP data.
The wobbling shape of the pregroove is similar to a sinusoid. The track excursion ranges within 0.03 um deviation of the tracking center. This range is 1/1000 of the wavelength of the pregroove. That's why it is called “wobbling”. Although the pregroove is almost invisible, the optical driving device of the CD-RW drive can detect it. This pregroove will introduce the laser beam of the CD-RW drive and provide the timing-related data, which are so-called ATIP data. The ATIP data can make the speed of the CD-RW stable during the writing process. That is, the optical driving device of the CD-RW drive can detect the pregroove and receive a wobble signal, then generates ATIP data to obtain the timing-related information.
Therefore, how to effectively read the wobble signal from the CD-RW and to effectively obtain the ATIP data from the wobble signal is an important issue in CD-RW application.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus for generating ATIP data by generating the ATIP clock signal to precisely generate the ATIP data.
The present invention is also directed to a method of generating ATIP data by generating the ATIP clock signal to precisely generate the ATIP data.
The present invention is directed to a method of generating ATIP data by using the bi-phase rule to generate the ATIP data when the ATIP data matches a synchronization pattern.
According to an embodiment of the present invention, the apparatus for generating an ATIP data is based on a wobble signal generated by reading a re-writable compact disc for generating an ATIP data. The apparatus comprises a frequency demodulator for demodulating the wobble signal to generate an original ATIP data signal (ATIPORG signal); an ATIP clock generating circuit for generating an ATIP clock signal (ATIPCLK signal) based on the wobble signal; and an ATIP data generating circuit, coupled to the frequency demodulator and the ATIP clock generating circuit, for generating the ATIP data based on the number of the ATIPORG signal at a first logic level during one period of the ATIPCLK signal.
In an embodiment of the present invention, the ATIP clock generating circuit includes: a counter for counting the wobble signal to generate the ATIPCLK signal to the ATIP data generating circuit and setting the period of the ATIPCLK signal to be 3.5 periods of the wobble signal; and an alignment signal generating circuit for detecting the ATIPORG signal, when the ATIPORG signal is kept at a same status within a predetermined period of time, the alignment signal generating circuit generates an alignment signal to align the ATIPCLK to the wobble signal with a status transition.
In an embodiment of the present invention, the frequency demodulator further comprises: a high frequency (HF) counter, for receiving the wobble signal and generating a plurality of counting data (FMPRD data) in each half-period of the wobble signal; and a low pass filter (LPF), for receiving the FMPRD data and filtering an average of half-period of the wobble signal; wherein the frequency demodulator subtracts the average of half-period of the wobble signal from the FMPRD data to obtain a plurality of differential data (PRDDIFF data), and the ATIPORG signal is determined by the PRDDIFF data in each half-period of the wobble signal: the ATIPORG signal is asserted to the first logic level when the PRDDIFF data in half-period of the wobble signal is positive or zero; and the ATIPORG signal is de-asserting to a second logic level when the PRDDIFF data in half-period of the wobble signal is negative.
In an embodiment of the present invention, the step of generating the ATIP data signal includes: demodulating a wobble signal to generate an original ATIP data signal (ATIPORG signal) and a plurality of differential data (PRDDIFF data), wherein the wobble signal is generated by reading a re-writable compact disc; generating an ATIP clock signal (ATIPCLK signal) based on the wobble signal; and counting the number of the ATIPORG signal at a first logic level during one period of the ATIPCLK signal.
In an embodiment of the present invention, the step of generating the ATIP data signal by using one predetermined threshold further includes: comparing the number of the ATIPORG signal at the first logic level with a predetermined threshold; asserting the ATIP data to the first logic level when the number of the ATIPORG signal at the first logic level is larger than or equal to the predetermined threshold; and de-asserting the ATIP data to a second logic level when the number of the ATIPORG signal at the first logic level is smaller than the predetermined threshold.
In an embodiment of the present invention, the step of generating the ATIP data signal by using two predetermined threshold further includes: adding all PRDDIFF data within the period of the ATIPCLK signal to obtain the adding data; comparing the number of the ATIPORG signal at the first logic level with a first predetermined threshold and a second predetermined threshold, and the first predetermined threshold is larger than the second predetermined threshold; asserting the ATIP data to the first logic level when the number of the ATIPORG signal at the first logic level is larger than the first predetermined threshold; and de-asserting the ATIP data to a second logic level when the number of the ATIPORG signal at the first logic level is smaller than the second predetermined threshold; when the number of the ATIPORG signal at the first logic level is between the first and the second predetermined thresholds: asserting the ATIP data to the first logic level when the adding data is positive; and de-asserting the ATIP data to the second logic level when the adding data is negative.
In an embodiment of the present invention, the step of demodulating the wobble signal to generate the ATIPORG signal further comprises: receiving the wobble signal and generating a plurality of counting data (FMPRD data) in each half-period of the wobble signal; filtering an average of half-period of the wobble signal from the FMPRD data; subtracting an average of a half-period of the wobble signal from the FMPRD data to obtain a plurality of differential data (PRDDIFF data) in each half-period of the wobble signal; and generating the ATIPORG signal based on the PRDDIFF data.
In an embodiment of the present invention, the step of generating the ATIPORG signal based on the PRDDIFF data comprises: asserting the ATIPORG signal at the first logic level when the PRDDIFF data is positive or zero; and asserting the ATIPORG signal at the second logic level when the PRDDIFF data is negative.
In an embodiment of the present invention, the step of generating the ATIPCLK signal based on the wobble signal comprises: counting the wobble signal to generate the ATIPCLK signal, the period of the ATIPCLK signal being 3.5 periods of the wobble signal; and aligning the ATIPCLK signal to the wobble signal with a status transition when the ATIPORG signal is kept at a same status within a predetermined period of time; wherein the predetermined period of time is an integral multiple of 3.5 periods of the wobble signal.
In an embodiment of the present invention, wherein the wobble signal is digitalized and processed by a de-glitch process.
In an embodiment of the present invention, the step of generating the ATIP data by using the bi-phase rule to generate the ATIP data when the ATIP data matches a synchronization pattern comprises: demodulating a wobble signal to generate an original ATIP data signal (ATIPORG signal) and a plurality of differential data (PRDDIFF data), wherein the wobble signal is generated by reading a re-writable compact disc; generating an ATIP clock signal (ATIPCLK signal) based on the wobble signal; defining the next period of the ATIPCLK signal to be a first period when a portion of the generated ATIP data matches a synchronization pattern (sync pattern); and generating an ATIP data based on the number of the ATIPORG signal at the first logic level corresponding to a 2Nth period of the ATIPCLK signal and the number of the ATIPORG signal at the first logic level corresponding to a 2N+1st period of the ATIPCLK signal, wherein N is a positive integer.
In an embodiment of the present invention, the step of generating the ATIP data further comprises: counting the number W1 of the ATIPORG signal at the first logic level, corresponding to the 2Nth period of the ATIPCLK signal; counting the number W2 of the ATIPORG signal at the first logic level, corresponding to the 2N+1st period of the ATIPCLK signal; adding the PRDDIFF data in the 2Nth period of the ATIPCLK signal to obtain an adding data S1; adding the PRDDIFF data in the 2N+1st period of the ATIPCLK signal to obtain an adding data S2; and determining the period of the ATIPCLK signal of the ATIP data is 2Nth period or 2N+1st period.
In an embodiment of the present invention, the step of generating the ATIP data further comprises: making the ATIP data be inverse of preceding period of the ATIPCLK signal when the period of the ATIPCLK signal is 2N+1st period; and comparing the number W1 and W2 when the period of the ATIPCLK signal is 2Nth period.
In an embodiment of the present invention, the step of generating the ATIP data further comprises: asserting the ATIP data to the first logic level when W1>W2; de-asserting the ATIP data to a second logic level when W1<W2; and comparing the adding data S1 and S2 when W1=W2.
In an embodiment of the present invention, the step of generating the ATIP data further comprises: asserting the ATIP data to the first logic level when S1>=S2; and de-asserting the ATIP data to the second logic level when S1<S2.
In light of the above, the present invention uses the status of the ATIPORG signal corresponding to the ATIPCLK signal and the bi-phase rule to precisely generate the ATIP data.
The above is a brief description of some deficiencies in the prior art and advantages of the present invention. Other features, advantages and embodiments of the invention will be apparent to those skilled in the art from the following description, accompanying drawings and appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is the block diagram of an apparatus for generating ATIP data in accordance with an embodiment of the present invention.
FIG. 2 is a timing sequence for generating the ATIP data in accordance with an embodiment of the present invention.
FIG. 3 is a timing sequence of an alignment signal in accordance with an embodiment of the present invention.
FIG. 4 is a timing sequence of generating an original ATIP data.
FIG. 5A is a flow chart of a method of generating ATIP data by using one predetermined threshold in accordance with an embodiment of the present invention.
FIG. 5B is a flow chart of a method of generating ATIP data by using two predetermined thresholds in accordance with an embodiment of the present invention.
FIG. 6 is a synchronization pattern in accordance with an embodiment of the present invention.
FIG. 7 is a flow chart of a method of generating ATIP data in accordance with an embodiment of the present invention by using the bi-phase rule.
FIG. 8 is a timing sequence of generating an ATIP data in accordance with an embodiment of the present invention by using the bi-phase rule.
FIG. 9 is a block diagram of the frequency demodulator.
DESCRIPTION OF THE EMBODIMENTS
Please reference to FIG. 1, which is the block diagram of an apparatus for generating ATIP data in accordance with an embodiment of the present invention. Generally, an optical driving device of the CD-RW drive detects pregrooves on an optical disc when processing recording the disc. At the mean time, the optical drive receives a wobble signal, which is a sinusoid. The optical drive need to generate an ATIP data from the wobble signal to obtain timing-related information from the disc. The wobble signal is a frequency-modulated signal. Please reference to FIG. 4, which is a timing sequence for generating the digital wobble signal by a comparing unit 102 in FIG. 1. To further illustrate how the digital wobble signal is generated so that one skilled in the art can easily understand, the relationship between the wobble signal and the digital wobble signal is little exaggeratedly illustrated in FIG. 4. Referring FIG. 4, because the wobble signal is frequency-modulated, the period of the wobble signal would vary. As a practical matter, the variation of the wobble signal is almost indistinguishable. When the comparing unit 102 receives the wobble signal, the comparing unit 102 compares the period of the wobble signal with an average half-period of the wobble signal. For example, during the time T0 to T1, the period of the wobble signal is larger than the average half-period of the wobble signal, so the digital wobble signal is at high logic level; during the time T1 to T2, the period of the wobble signal is smaller than the average half-period of the wobble signal, so the digital wobble signal is at low logic level. The wobble signal usually has some noise on it, so a de-glitch circuit 101 is for eliminating the glitches of the digital wobble signal and generating a de-glitch wobble signal (DEWBL signal). In practice, the DEWBL signal is illustrated in FIG. 2, the variation of the period of the DEWBL signal is very limited.
Since the wobble signal is a frequency-modulated signal, so it needs to be de-modulated by a frequency modulator. Please reference to FIGS. 1, 2 and 9, and FIG. 9 is the block diagram of a frequency demodulator 103 shown in FIG. 1. In this embodiment, a high frequency (HF) counter 901 receives the DEWBL signal and generates a plurality of counting data (FMPRD data) in each half-period of the DEWBL signal. Then, the FMPRD data are transferred to a low pass filter (LPF) 903 for filtering an average of half-period of the DEWBL signal. The average of half-period of the DEWBL signal is subtracted from the FMPRD data to generate a plurality of differential data (PRDDIFF data) in each half-period of the DEWBL signal. The PRDDIFF data are transferred to an ATIP data generating circuit 105, see in FIG. 1. In addition, the frequency demodulator 103 generates the original ATIP data signal (ATIPORG signal) which is determined by the PRDDIFF data in each half-period of the DEWBL signal. If the PRDDIFF data in half-period of the DEWBL signal is positive or zero, the ATIPORG signal is at high logic level; if the PRDDIFF data in half-period of the DEWBL signal is negative, the ATIPORG signal is at low logic level, see in FIG. 2. The ATIPORG signal is also transferred to the ATIP data generating circuit 105.
The apparatus in FIG. 1 further includes an ATIP clock generating circuit 110 for generating an ATIP clock signal (ATIPCLK signal) based on the DEWBL signal and for transferring the ATIPCLK signal to the ATIP data generating circuit 105. The ATIP clock generating circuit 110 includes a counting circuit 112 and an alignment signal generating circuit 114. The counting circuit 112 receives the DEWBL signal and counts the clock period of the DEWBL signal. When the DEWBL signal oscillates 3.5 periods, the counting circuit 112 generates a period of ATIPCLK signal. That is, a period of ATIPCLK signal is generated in every 3.5 period of the DEWBL signal. The design of the ATIP clock generating circuit 110 is in order to meet the compact disc specification. The compact disc specification defines that 1-bit ATIP data is generated in every 3.5 period of the wobble signal. That's the reason why the ATIP clock generating circuit 110 is designed in this way. As for the alignment signal generating circuit 114, which is for aligning the ATIPCLK signal with the DEWBL signal in long time duration to ensure the ATIP data generated from ATIP data generating circuit 105 is accurate based on the ATIPCLK signal. The alignment signal generating circuit 114 receives the ATIPORG signal and the DEWBL signal, and monitors the ATIPORG signal. When the ATIPORG signal is kept at the same logic level in a predetermined time period, the alignment signal generating circuit 114 generates an alignment signal (ALIGN signal) as shown in FIG. 3. FIG. 3 is a timing sequence of an alignment signal in accordance with an embodiment of the present invention. Referring to FIG. 1 and FIG. 3, in this embodiment, during the seven consecutive periods of the DEWBL signal (time T1 through time T2), because the ATIPORG signal is kept at low logic level, the ALIGN signal is generated at time T2 and is sent to the counting circuit 112 so that the ATIPORG signal is aligned with the DEWBL signal at time T2 (at time T2 the ATIPCLK signal makes a transition).
Referring to FIG. 1, the ATIP data generating circuit 105 is coupled to the frequency demodulator 103 and the ATIP clock generating circuit 110. The ATIP data generating circuit 105 also receives the PRDDIFF data, the ATIPORG signal and the ATIPCLK signal, and also generates the ATIP data based on the ATIPORG signal and the ATIPCLK signal. As above mentioned, the compact disc specification defines that 1-bit ATIP data is generated in every 3.5 period of the wobble signal. Please see FIG. 2, an ATIPCLK signal is generated in time T0 to T1 (3.5 period of the de-glitch wobble signal), but the ATIPORG signal is at high logic level when the PRDDIFF data is positive or zero, the ATIPORG signal is at low logic level when the PRDDIFF data is negative, so 1-bit ATIP data in time T0 to T1 is hard to decide to be at high logic level or low logic level. There are two ways provided in the present invention to generate the 1-bit ATIP data in every 3.5 period of the DEWBL signal.
Method 1
FIG. 5A is a flow chart of the method of generating ATIP data using one predetermined threshold in accordance with an embodiment of the present invention. In FIG. 5A, the method includes demodulating a de-glitch wobble signal (DEWBL signal) to generate an original ATIP data signal (ATIPORG signal) and a plurality of differential data (PRDDIFF data) (S501), and then generating an ATIP clock signal (ATIPCLK signal) based on the DEWBL signal (S503). One period of the ATIPCLK signal is generated in every 3.5 period of the DEWBL signal.
Referring to FIG. 1 and FIG. 5A, when the ATIP data generating circuit 105 receives the ATIPORG signal and the ATIPCLK signal, then generates the ATIP data by counting the number of the ATIPORG signal at high logic level (low logic level) during one period of the ATIPCLK signal (S512). For example, the ATIPORG signal in time T0 to T1 in FIG. 2, the number of the ATIPORG signal at high logic level is 5 (corresponding to +1, +3, +4, +1, +2), and the number of the ATIPORG signal at low logic level is 2 (corresponding to −1, −2). Next, comparing the number of the ATIPORG signal at high logic level (low logic level) with a predetermined threshold THR1 (S514), for example, THR1 is 4. If the number of the ATIPORG signal at high logic level (low logic level) is larger than or equal to THR1, the ATIP data is asserted (de-asserted) to high logic level (low logic level) (S516); if the number of the ATIPORG signal at high logic level (low logic level) is smaller than THR1, the ATIP data is de-asserted (asserted) to low logic level (high logic level) (S518). In above mentioned example, the number of the ATIPORG signal at high logic level is 5, which is larger than the predetermined threshold 4, so the 1-bit ATIP data in time T0 to T1 is asserted to high logic level. Above described case is for only one threshold to generate the ATIP data.
Two thresholds are provided to be used in the present invention. Please reference to FIG. 5B, which is a flow chart of a method of generating ATIP data in using two predetermined thresholds in accordance with an embodiment of the present invention. Similarly, the method includes demodulating a DEWBL signal to generate an ATIPORG signal and PRDDIFF data (S501), and then generating an ATIPCLK signal based on the DEWBL signal (S503). One period of the ATIPCLK signal is generated in every 3.5 period of the DEWBL signal. Referring to FIG. 1 and FIG. 5B, when the ATIP data generating circuit 105 receives the ATIPORG signal and the ATIPCLK signal, then generates the ATIP data by counting the number of the ATIPORG signal at high logic level (low logic level) during one period of the ATIPCLK signal (S512). For example, the ATIPORG signal in time T1 to T2 in FIG. 2, the number of the ATIPORG signal at high logic level is 4 (corresponding to +1, +1, +2, +1), and the number of the ATIPORG signal at low logic level is 3 (corresponding to −4, −3, −2). Then, all PRDDIFF data are added within the period of the ATIPCLK signal to obtain the adding data S (S523). For example, the adding data S added within the time T1 to T2 is 4. Next, comparing the number of the ATIPORG signal at high logic level (low logic level) with two predetermined thresholds THR1 and THR2, wherein THR1 is larger than THR2 (S525). In the embodiment, THR1 is 5 and THR2 is 2. If the number of the ATIPORG signal at high logic level (low logic level) is larger than THR1, the ATIP data is asserted (de-asserted) to high logic level (low logic level) (S527). If the number of the ATIPORG signal at high logic level (low logic level) is lower than THR2, the ATIP data is de-asserted (asserted) to low logic level (high logic level) (S529). If the number of the ATIPORG signal at high logic level (low logic level) is between the threshold THR1 and THR2, then determining the adding data S is positive or negative (S531). If the adding data S is positive, the ATIP data is asserted to high logic level (S533). If the adding data S is negative, the ATIP data is de-asserted to low logic level (S535). In above mentioned example, the number of the ATIPORG signal at high logic level is 4, THR2 (2)<4<THR1 (5), so it needs to determining the adding data S is positive or negative. In this example, the adding data S is −4 (<0) during the time T1 and T2. Hence, the ATIP data is de-asserted to low logic level during the time T1 to T2. This is the first method of generating 1-bit ATIP data during one period of ATIP clock signal ATIPCLK.
Method 2
Para FIG. 6 is the synchronization pattern (sync pattern) in accordance with an embodiment of the present invention. The sync pattern represents the start of the disc data. The format of sync pattern is 3T-1T-1T-3T. When a sync pattern is detected, the data after the sync pattern must follow the bi-phase rule which is defined in compact disc specification. The bi-phase rule defines two things: one is that the first bit after the sync pattern must be inverse of the preceding bit, which is marked A in FIG. 6, the other thing is that the second (2Nth) bit after the sync pattern must be different from the next (2N+1st) bit, which is marked B in FIG. 6. Therefore, when the sync pattern 3T-1T-1T-3T is found that in the ATIP data, the bi-phase rule must be followed to generate the ATIP data. The synchronization pattern provided by the present invention is shown in FIG. 6, more particularly, when the ATIP data is kept at high logic level for three consecutive periods, the ATIP data will be at low logic level for the next period, at the high logic level for next period, and at low logic level for the next three consecutive periods. Although the present invention provides the above synchronization pattern, it should not be used to limit the scope of the present invention.
FIG. 7 is a flow chart of a method of generating ATIP data in accordance with an embodiment of the present invention by using the bi-phase rule. Referring to FIG. 7, the first step is demodulating a DEWBL signal to generate an ATIPORG signal and PRDDIFF data (S701), and then generating an ATIPCLK signal based on the DEWBL signal (S703). One period of the ATIPCLK signal is generated in every 3.5 period of the DEWBL signal. When a portion of the generated ATIP data matches a sync pattern (3T-1T-1T-3T), defining the next period of the ATIPCLK signal to be a first period (S705). Next, generating the ATIP data based on the number of the ATIPORG signal at high logic level corresponding to a 2Nth period of the ATIPCLK signal and the number of the ATIPORG signal at high logic level corresponding to a 2N+1st period of the ATIPCLK signal (S710), wherein N is a positive integer.
The step S710 further includes the following steps. Counting the number W1 of the ATIPORG signal at high logic level (low logic level) corresponding to a 2Nth period of the ATIPCLK signal (S712) and counting the number W2 of the ATIPORG signal at high logic level (low logic level) corresponding to a 2N+1st period of the ATIPCLK signal (S714). Then, adding the PRDDIFF data in the 2Nth period of the ATIPCLK signal to obtain an adding data S1 (S721) and adding the PRDDIFF data in the 2N+1st period of the ATIPCLK signal to obtain an adding data S2 (S723). Next, determining the period of the ATIPCLK signal of the ATIP data is 2Nth period or 2N+1st period (S725). If the period of the ATIPCLK signal is 2N+1st period, make the ATIP data be inverse of preceding period of the ATIPCLK signal (S727). If the period of the ATIPCLK signal is 2Nth period, comparing the number W1 and W2 (S731). If W1>W2, the ATIP data is asserted to high logic level (S733). If W1<W2, the ATIP data is de-asserted to low logic level (S735). If W1=W2, comparing the adding data S1 and S2 (S737). If S1 >=S2, the ATIP data is asserted to high logic level (S739). If S1<S2, the ATIP data is de-asserted to low logic level (S741).
FIG. 8 is a timing sequence of generating the ATIP data signal in accordance with an embodiment of the present invention by using the bi-phase rule. When a portion of the generated ATIP data matches a sync pattern (3T-1T-1T-3T) shown in FIG. 6, defining the next period of the ATIPCLK signal to be a first period. The ATIP data in the first period of the ATIPCLK signal is the inverse of the preceding period of the ATIP data. Next, counting the number W1 of the ATIPORG signal at high logic level corresponding to a 2Nth period of the ATIPCLK signal (e.g., the EVEN period in time T0 to T1) and counting the number W2 of the ATIPORG signal at high logic level corresponding to a 2N+1st period of the ATIPCLK signal (e.g., the ODD periods in time T1 to T2). W1 is 5 and W2 is 2. Then, adding the PRDDIFF data in the 2Nth period of the ATIPCLK signal (e.g., the EVEN periods in time T0 to T1) to obtain an adding data S1 and adding the PRDDIFF data in the 2N+1st period of the ATIPCLK signal (e.g., the ODD period in time T1 to T2) to obtain an adding data S2. S1 is 8 and S2 is −4. If the period of the ATIPCLK signal is 2Nth period (e.g., the EVEN period in time T0 to T1), comparing the number W1 and W2. Due to W1 is 5 and W2 is 2, so W1>W2, the ATIP data in time T0 to T1 is asserted to high logic level. If the period of the ATIPCLK signal is 2N+1st period (e.g., the ODD periods in time T1 to T2), make the ATIP data be inverse of preceding period of the ATIPCLK signal. In this embodiment, the ODD period is at low logic level which is the inverse of the preceding EVEN period of the ATIP data.
If the condition W1=W2 happens, comparing the adding data S1 and S2. Assume the W1 and W2 is equal in FIG. 6, comparing the adding data S1 and S2. Since S1 is 8 and S2 is −4, so S1>S2, the ATIP data in time T0 to T1 is asserted to high logic level.
In light of the above, the present invention uses the status of the ATIPORG signal corresponding to the ATIPCLK signal and the bi-phase rule to precisely generate the ATIP data.
The above description provides a full and complete description of the preferred embodiments of the present invention. Various modifications, alternate construction, and equivalent may be made by those skilled in the art without changing the scope or spirit of the invention. Accordingly, the above description and illustrations should not be construed as limiting the scope of the invention which is defined by the following claims.
Patent Application
20090103402
