METHOD AND APPARATUS FOR GENERATING PSEUDO-RANDOM SEQUENCE, ELECTRONIC DEVICE, AND STORAGE MEDIUM

Abstract

A method and an apparatus for generating a pseudo-random sequence, an electronic device, and a computer-readable storage medium. The method for generating a pseudo-random sequence comprises: performing an AND operation and an XOR operation on M bit values of a first sequence to obtain an (A+m)th bit value of the first sequence; where M is an integer greater than or equal to 1, and A is an integer greater than or equal to 0 (100); and determining, according to the (A+m)th bit value of the first sequence, an mth bit value of the pseudo-random sequence (101).

Description

The present application is based on and claims a priority from the Chinese patent application No. 202010765593.6 filed on Jul. 31, 2020, the entire disclosure of which is incorporated herein by reference.

TECHNICAL FIELD

Embodiments of the present application relate to the field of communications, and in particular, to a method and an apparatus for generating a pseudo-random sequence, an electronic device, and a computer-readable storage medium.

BACKGROUND

The pseudo-random sequence, due to good randomness and related functions close to white noise and capabilities of being able to be pre-determined and repeated, is widely applied in the fields of channel estimation, signal scrambling, frequency hopping and the like in communication systems.

The 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) or New Radio (NR) standard adopts a Gold sequence as a pseudo-random sequence, and currently, the occupied memory volume or execution time will increase with a length of the sequence during generation of the Gold sequence, thereby affecting the performance of the device.

SUMMARY

Embodiments of the present application provide a method and an apparatus for generating a pseudo-random sequence, an electronic device, and a computer-readable storage medium.

In a first aspect, an embodiment of the present application provides a method for generating a pseudo-random sequence, including: performing an AND operation and an XOR operation on M bit values of a first sequence to obtain an (A+m)^th bit value of the first sequence; where M is an integer greater than or equal to 1, and A is an integer greater than or equal to 0; and determining, according to the (A+m)^th bit value of the first sequence, an m^th bit value of the pseudo-random sequence.

In a second aspect, an embodiment of the present application provides an electronic device, including: at least one processor, and a memory having at least one program stored thereon which, when executed by the at least one processor, causes the at least one processor to implement any method for generating a pseudo-random sequence as described above.

In a third aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon which, when executed by a processor, causes any method for generating a pseudo-random sequence as described above to be implemented.

In a fourth aspect, an embodiment of the present application provides an apparatus for generating a pseudo-random sequence, including: a calculation module configured to calculate, according to an initial value of a first sequence, M bit values of the first sequence; where M is an integer greater than or equal to 1; a logic operation module configured to perform an AND operation and an XOR operation on the M bit values to obtain an (A+m)^th bit value of the first sequence; where A is an integer greater than or equal to 0; and a determination module configured to determine, according to the (A+m)^th bit value of the first sequence, an m^th bit value of the pseudo-random sequence.

In the method for generating a pseudo-random sequence provided in the embodiments of the present application, an AND operation and an XOR operation are simply performed on M bit values of a first sequence to obtain an (A+m)^th bit value of the first sequence, and thus an m^th bit value of the pseudo-random sequence. Since the AND operation and the XOR operation are both simple logic operations, the storage space and processor resources are saved, while the operation speed is increased, thereby improving performance of the device.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a flowchart of a method for generating a pseudo-random sequence according to an embodiment of the present application;

FIG. 2 is a schematic diagram illustrating an AND operation and an XOR operation performed according to an embodiment of the present application; and

FIG. 3 is a block diagram of an apparatus for generating a pseudo-random sequence according to another embodiment of the present application.

DETAIL DESCRIPTION OF EMBODIMENTS

In order to make those skilled in the art better understand the technical solutions of the present application, the following describes the method and apparatus for generating a pseudo-random sequence, the electronic device, and the computer-readable storage medium of the present application in detail with reference to the accompanying drawings.

Example embodiments will be described more sufficiently below with reference to the accompanying drawings, but which may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present application will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

The embodiments of the present application and features thereof may be combined with each other as long as they are not contradictory.

As used herein, the term “and/or” includes any and all combinations of at least one associated listed item.

The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the present application. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that as used herein, the terms “comprise” and/or “consist of ...” specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of at least one other feature, integer, step, operation, element, component, and/or group thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the existing art and the present application, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The pseudo-random sequence adopted by 3GPP LTE or NR is a 31-bit Gold sequence, and is configured to produce polynomials of the 31-bit Gold sequence, such as formulas (1) to (3):

$\begin{array}{cc}c\left(n\right)=\left[x_1\left(n+N_c\right)+x_2\left(n+N_c\right)\right]\mathrm{mod}2& \text{­­­(1)}\end{array}$

$\begin{array}{cc}{x}_1\left(n+31\right)=\left[x_1\left(n+3\right)+x_1\left(n\right)\right]\mathrm{mod}2& \text{­­­(2)}\end{array}$

$\begin{array}{cc}{x}_2\left(n+31\right)=\left[x_2\left(n+3\right)+x_2\left(n+2\right)+x_2\left(n+1\right)+x_2\left(n\right)\right]\mathrm{mod}2& \text{­­­(3)}\end{array}$

where Nc = 1600.

According to the polynomial iterative relations (1) to (3), the sequence c (n) is calculated from x₁(n+N_c) and x₂(n+N_c), and x₁ is initialized to: x₁(0) = 1, x₁(n) = 0; n =1,2,3...30; An initialization value of x₂ is calculated from c_init, i.e.,

$c_{init}={\displaystyle \sum _{i=0}^{30}{x}_2\left(i\right)\cdot 2^i};$

then a sequence x₁(n+N_c) and a sequence x₂(n+N_c), and thus a final c(n) sequence, are obtained.

Currently, there are two methods for generating a pseudo-random sequence.

A first method includes: inputting initial values of x₁ and x₂, and calculating all sequences iteratively one by one according to the polynomial iterative relations (1) to (3), which may be implemented by software or hardware. This method occupies less device resources (including memory resources and processor resources), but has a lower calculation speed, and is not beneficial to real-time calculation.

A second method includes: obtaining an initial state sequence V0 from the initial values of x₁ and x₂, deriving a one-step state transition matrix M from a current state sequence to a next state sequence according to the iterative formulas, where the next state sequence may be obtained by multiplying the current state sequence by M, and generating all the sequences in a similar manner:

$V1=V_{0}M;$

$V_2=V_{1}M=V_0{M}^2;$

...

$V_k=V_{k-1}M=V_0{\displaystyle \prod _1^{k}M=V_0{M}^k}.$

An advantage of the second method is that a parallel processing computing power of the multi-operation unit is utilized, and 32-bits can be computed simultaneously; and a disadvantage of this method is that k power of M is desired to be calculated, which involves a large amount of accumulation and product calculation, wastes a large amount of storage space and processor resources, and thus influences performance of the device.

FIG. 1 is a flowchart of a method for generating a pseudo-random sequence according to an embodiment of the present application.

In a first aspect, referring to FIG. 1, an embodiment of the present application provides a method for generating a pseudo-random sequence, including the following operations 100 to 101.

At operation 100, performing an AND operation and an XOR operation on M bit values of a first sequence to obtain an (A+m)^th bit value of the first sequence; where M is an integer greater than or equal to 1, and A is an integer greater than or equal to 0.

In some exemplary embodiments, M is less than or equal to a bit width of a processor. The optimal performance is achieved when the value of M is equal to the bit width of the processor. For example, when the bit width of the processor is 32, M may be any one of 4, 8, 16, and 32, but the optimal performance is achieved when M is 32. Other situations are similar.

In some exemplary embodiments, the M bit values include: a j^th bit value to a (j+M-1)^th bit value; where j is an integer greater than or equal to 0. For example, the M bit values include a 0^th bit value to an (M-1)^th bit value, ora 1^st bit value to an M^th bit value. The specific M bit values are not particularly limited in the embodiments of the present application.

In some exemplary embodiments, if the pseudo-random sequence to be generated is a Gold sequence, the first sequence may be an x₂ sequence. If the pseudo-random sequence to be generated is another sequence, the first sequence may also be another sequence. The specific form of the first sequence is not particularly limited in the embodiments of the present application.

In some exemplary embodiments, performing the AND operation and the XOR operation on M bit values of the first sequence to obtain the (A+m)^th bit value of the first sequence includes:

performing an AND operation on an i^th bit value in the M bit values and k_(m.i) to obtain a corresponding i^th intermediate bit value; where i is an integer greater than or equal to 1 and less than or equal to M, and k_(m.i) is a proportionality coefficient corresponding to the i^th bit value and m; and m is an integer greater than or equal to 0; and performing an XOR operation on M intermediate bit values to obtain the (A+m)^th bit value of the first sequence.

In some exemplary embodiments, a value of k_(m.i) is determined from an original proportionality coefficient of x₂(i) split from x₂(A+m), and when the original proportionality coefficient of x₂(i) split from x₂(A+m) is an even number, the value of k_(m.i) is 0; when the original proportionality coefficient of x₂(i) split from x₂(A+m) is an odd number, the value of k_(m.i) is 1.

FIG. 2 is a schematic diagram of an AND operation and an XOR operation taking M being 32 as an example. As shown in FIG. 2, 32 bit values are input and subjected to an AND operation with 32 k values in a bitwise manner to obtain 32 intermediate bit values, and the 32 intermediate bit values are subjected to an XOR operation obtain the (A+m)^th bit value.

In some exemplary embodiments, if the pseudo-random sequence is a Gold sequence, A may take a value Nc, i.e., 1600. If the pseudo-random sequence is another sequence, A may also take another value. The specific value may be determined according to the actual situation, as long as the value of A can satisfy calculation of the 1^st bit value of the pseudo-random sequence. For the Gold sequence, since the 1^st bit value of the Gold sequence is calculated from x₂(Nc), A taking the value of Nc is most efficient for calculation. Apparently, A may also take a value other than Nc, but further iterative calculation is required to obtain the 1^st bit value of the Gold sequence.

In some exemplary embodiments, before performing the AND operation on the i^th bit value in the M bit values and k_(m.i) to obtain the corresponding i^th intermediate bit value, the method further includes: determining k_(m.i) according to a first correspondence relationship among i, m and k_{(m.i) .}

In some exemplary embodiments, the first correspondence relationship may be implemented in various expressions, for example, in the form of a two-dimensional table, or in the form of a two-dimensional array, or in the form of a two-dimensional matrix. If a two-dimensional table is used, rows of the table may be i and columns may be m; alternatively, rows of the table may be m and columns may be i; and each cell is a corresponding value of k_(m.i) . Other situations are similar and are not repeated here.

In some exemplary embodiments, the AND operation and the XOR operation may be performed in a serial manner or in a parallel manner. In the parallel manner, an operation unit of the processor is sufficiently utilized, so that the pseudo-random sequence can be rapidly generated in real time, thereby saving the storage space, and improving the generation efficiency of the pseudo-random sequence. For example, in the case of 4 operation units, through timing analysis and according to the optimal 4 segments, the result of 4 bits can be calculated within 1 clock cycle. In other words, for the first sequence, the AND operations of 4 M-bit values can be performed simultaneously, thereby increasing the operation speed.

In some exemplary embodiments, performing the AND operation and the XOR operation in a parallel manner may specifically include: performing the AND operation and the XOR operation corresponding to m corresponding to a same segment in parallel. Each segment includes N bit values, and N is an integer greater than or equal to 2; and the segment is obtained by dividing the pseudo-random sequence.

In other words, the pseudo-random sequence is divided into at least one segment, each segment includes N bit values of the pseudo-random sequence. The calculation processes of the N bit values belonging to a same segment are performed in parallel, and the calculation process of each bit value includes an AND operation, an XOR operation, and operation 102.

In some exemplary embodiments, N is less than or equal to a maximum parallel number supported by a processor.

The Gold sequence is taken as an example to explain why the (A+m)^th bit value of the first sequence can be obtained by performing an AND operation and an XOR operation on M features. Although the Gold sequence is taken as an example for description here, the method provided in the embodiments of the present application may also be used in generation of other pseudo-random sequences.

From the recursion formula x₂(n+31)=[x₂(n+3)+x₂(n+2)+x₂(n+1)+x₂(n)]mod2 for the x₂ sequence, x₂ (1570 + 31) can be calculated, i.e.,:

$\begin{array}{l}{x}_2\left(1601\right)=\left[x_2\left(1573\right)+x_2\left(1572\right)+x_2\left(1571\right)+x_2\left(1570\right)\right]\mathrm{mod}2\\ =\left\{\begin{array}{l}\left[x_2\left(1545\right)+x_2\left(1544\right)+x_2\left(1543\right)+x_2\left(1542\right)\right]\mathrm{mod}2+\\ \left[x_2\left(1544\right)+x_2\left(1543\right)+x_2\left(1542\right)+x_2\left(1541\right)\right]\mathrm{mod}2+\\ \left[x_2\left(1543\right)+x_2\left(1542\right)+x_2\left(1541\right)+x_2\left(1540\right)\right]\mathrm{mod}2+\\ \left[x_2\left(1542\right)+x_2\left(1541\right)+x_2\left(1540\right)+x_2\left(1539\right)\right]\mathrm{mod}2+\end{array}\right\}\mathrm{mod}2.\end{array}$

Since the mod2 operation reflects a parity of the result, the mod2 operation can be performed again by adding all bits together, so

$\begin{array}{l}{x}_2\left(1601\right)=\\ \left[\begin{array}{l}{x}_2\left(1545\right)+2\times x_2\left(1544\right)+3\times x_2\left(1543\right)+4\times x_2\left(1542\right)+\\ 3\times x_2\left(1541\right)+2\times x_2\left(1540\right)+x_2\left(1539\right)\end{array}\right]\mathrm{mod}2.\end{array}$

The above formula may be equivalent to firstly performing mod2 operation on k_i×₂(i) before adding, and finally performing the mod2 operation for a further time. Therefore, the above formula may be rewritten as:

$x_2(1601)=\left\{\begin{array}{l}[x_2(1545)]\mathrm{mod}2+[2\times x_2(1544)]\mathrm{mod}2+(1543)]\mathrm{mod}2+\\ [4\times x_2(1542)]\mathrm{mod}2+(3\times x_2(1541)]\mathrm{mod}2+\\ [2\times x_2(1540)]\mathrm{mod}2+[x_2(1539)]\mathrm{mod}2\end{array}\right\}\mathrm{mod}2.$

For

$\left[k_i\times x_2\left(n\right)\right]\mathrm{mod}2,$

, since

$\left[{\text{k}}_{\text{i}}\times x_2\left(\text{n}\right)\right]\mathrm{mod}2=\left({\text{k}}_{\text{i}}\mathrm{mod}2\right)\times \left[x_2\left(n\right)\mathrm{mod}2\right],$

if k_i (i.e., the original proportionality coefficient) is even, then

$\left[{\text{k}}_{\text{i}}\times x_2\left(\text{n}\right)\right]\mathrm{mod}2=0;$

and if ki is odd, then

$\left[{\text{k}}_{\text{i}}\times x_2\left(\text{n}\right)\right]\mathrm{mod}2=x_2\left(\text{n}\right)\mathrm{mod}2.$

Therefore, the above formula may be simplified to:

$\begin{array}{l}{x}_2\left(1601\right)=\\ \left\{\begin{array}{l}\left[x_2\left(1545\right)\right]\mathrm{mod}2+\left[x_2\left(1543\right)\right]\mathrm{mod}2+\\ \left[x_2\left(1541\right)\right]\mathrm{mod}2+\left[x_2\left(1539\right)\right]\mathrm{mod}2\end{array}\right\}\mathrm{mod}2\end{array}$

.

Then, x₂(1545), x₂(1543), x₂(1541) and x₂(1539) may be further split, and finally x₂(1601) is split into a combination of

$x_2\left(\text{n}\right),\text{n}\in \left[0,\text{M-1}\right],$

so:

$x_2\left(N_C+m\right)=\left[{\displaystyle \sum _{i=0}^{M-1}{k}_{\left(m,i\right)}*x_2\left(i\right)}\right]\mathrm{mod}2;$

where Nc = 1600, k(mi)∈[0,1], and x₂(i) ∈ [0,1], and

$y_{\left(m,i\right)}=k_{\left(m,i\right)}*x_2\left(i\right)$

may be implemented through an AND operation of (M-1) bits in a bitwise manner. That is,

$y_{\left(m,i\right)}=k_{\left(m,i\right)}*x_2\left(i\right)$

is equivalent to

$y_{\left(m,i\right)}=k_{\left(m,i\right)}*\&x_2\left(i\right),$

and denoted by y(m.i), and since [x₂(i)+x₂(i+1)]mod2 is equivalent to

$x_2\left(i\right)^x_2\left(i+1\right),$

x2(Nc+m) may be implemented by an XOR operation, so:

$x_2\left(N_C+m\right)=\left[{\displaystyle \sum _{i=0}^{\text{M-1}}y\left(m,i\right)}\right]\mathrm{mod}2=y_{\left(m,0\right)^}{y}_{\left(m,1\right)^}{y}_{\left(m,2\right)\dots ^}{y}_{\left(m,\text{M-1}\right)};$

where ^ represents the XOR operation. That is, obtaining the (A+M)^th bit value of the first sequence involves firstly performing an AND operation on bit values of the M bits in a bitwise manner, and then performing an XOR operation on results of the AND operation of the M bits, to obtain the (A+m)^th bit value of the first sequence, and thus an output of 1 bit value of the pseudo-random sequence.

At operation 101, determining, according to the (A+m)^th bit value of the first sequence, an m^th bit value of the pseudo-random sequence.

In some exemplary embodiments, determination of N bit values belonging to a same segment in the pseudo-random sequence is performed in parallel.

In some exemplary embodiments, before performing the AND operation and the XOR operation on M bit values of the first sequence to obtain the (A+m)^th bit value of the first sequence, the method further includes:

calculating, according to an initial value of the first sequence, M bit values of the first sequence.

The following describes the calculation process of M bit values by taking a pseudo-random sequence being a Gold sequence as an example.

First, the 0^th bit value to the 30^th bit value, that is, an initial value of the first sequence, is calculated from tan initial value c_init. Specifically, the calculation is performed according to formula

$c_{init}={\displaystyle \sum _{i=0}^{30}{x}_2\left(i\right)\cdot 2^i}$

.

Second, if there is a bit value having a position in the first sequence greater than 30 among the M bit values, the bit value having a position in the first sequence greater than 30 is calculated according to recursion formula

$x_2\left(n+31\right)=\left[x_2\left(n+3\right)+x_2\left(n+2\right)+x_2\left(n+1\right)+x_2\left(n\right)\right]\mathrm{mod}2.$

In some exemplary embodiments, before determining, according to the (A+m)^th bit value of the first sequence, the m^th bit value of the pseudo-random sequence, the method further includes: acquiring, according to a preset second correspondence relationship between i and an i^th bit value of a second sequence, an (A+m)^th bit value of the second sequence; where i is an integer greater than or equal to 1 and less than or equal to M.

Accordingly, determining, according to the (A+m)^th bit value of the first sequence, the m^th bit value of the pseudo-random sequence includes: determining, according to the (A+m)^th bit value of the first sequence and the (A+m)^th bit value of the second sequence, the m^th bit value of the pseudo-random sequence.

In some exemplary embodiments, if the pseudo-random sequence is a Gold sequence, the second sequence may be an x₁ sequence. Each bit value in the x₁ sequence may be calculated from the recursion formula

$x_1\left(n+31\right)=\left[x_1\left(n+3\right)+x_1\left(n\right)\right]\mathrm{mod}2,$

and stored, and directly called when a certain bit value of the second sequence is desired to be obtained.

In some exemplary embodiments, the second correspondence relationship may be implemented in various expressions, for example, in the form of a one-dimensional table, or in the form of a one-dimensional array, or in the form of a one-dimensional matrix. If a one-dimensional table is used, rows or columns of the table may be i; and a unit cell corresponding to each row or column is the i^th bit value of the second sequence. Other situations are similar and are not repeated here.

In some exemplary embodiments, if the pseudo-random sequence is a Gold sequence, the m^th bit value of the pseudo-random sequence is calculated from recursion formula

$c\left(n\right)=\left[x_1\left(n+N_C\right)+x_2\left(n+N_C\right)\right]\mathrm{mod}2.$

In the method for generating a pseudo-random sequence provided in the embodiments of the present application, M bit values of the first sequence are firstly calculated, and then subjected to an AND operation and an XOR operation to obtain an (A+m)^th bit value of the first sequence, and thus an m^th bit value of the pseudo-random sequence. Since the AND operation and the XOR operation are both simple logic operations, the storage space and processor resources are saved, while the operation speed is increased, thereby improving performance of the device.

It should be noted that the method for generating a pseudo-random sequence provided in the embodiments of the present application may be implemented by software or hardware, for example, by an AND gate and an XOR gate.

In a second aspect, an embodiment of the present application provides an electronic device, including:

• at least one processor, and
• a memory having at least one program stored thereon which, when executed by the at least one processor, causes the at least one processor to implement any method for generating a pseudo-random sequence as described above.

The processor is a device having a data processing capability, including but not limited to a central processing unit (CPU), or the like. The memory is a device with a data storage capability including but not limited to, a random access memory (RAM, more specifically SDRAM, DDR, etc.), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM) or a flash.

In some embodiments, the processor and the memory are connected to each other via a bus, and further connected to other components of a computing device.

In a third aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon which, when executed by a processor, causes any method for generating a pseudo-random sequence as described above to be implemented.

FIG. 3 is a block diagram of an apparatus for generating a pseudo-random sequence according to another embodiment of the present application.

In a fourth aspect, referring to FIG. 3, another embodiment of the present application provides an apparatus for generating a pseudo-random sequence, including:

• a calculation module 301 configured to calculate, according to an initial value of a first sequence, M bit values of the first sequence, where M is an integer greater than or equal to 1;
• a logic operation module 302 configured to perform an AND operation and an XOR operation on the M bit values to obtain an (A+m)^th bit value of the first sequence, where A is an integer greater than or equal to 0; and
• a determination module 303 configured to determine, according to the (A+m)^th bit value of the first sequence, an m^th bit value of the pseudo-random sequence.

In some exemplary embodiments, the logic operation module 302 is specifically configured to:

perform an AND operation on an i^th bit value in the M bit values and k_(m.i) to obtain a corresponding i^th intermediate bit value; where i is an integer greater than or equal to 1 and less than or equal to M, and k_(m.i) is a proportionality coefficient corresponding to the i^th bit value and m; and m is an integer greater than or equal to 0; and perform an XOR operation on M intermediate bit values to obtain the (A+m)^th bit value of the first sequence.

In some exemplary embodiments, the logic operation module 302 is further configured to:

determine k_(m.i) according to a first correspondence relationship among i, m and k_(m.i)

In some exemplary embodiments, the AND operation and the XOR operation corresponding to m of a same segment are performed in parallel, and determination of bit values belonging to a same segment in the pseudo-random sequence is performed in parallel. Each segment includes N bit values, and N is an integer greater than or equal to 2; and the segment is obtained by dividing the pseudo-random sequence.

In some exemplary embodiments, N is less than or equal to a maximum parallel number supported by a processor.

In some exemplary embodiments, M is less than or equal to a bit width of a processor.

In some exemplary embodiments, the M bit values include: a j^th bit value to a (j+M-1)^th bit value; where j is an integer greater than or equal to 0.

In some exemplary embodiments, the apparatus further includes: an acquisition module 304 configured to acquire, according to a preset second correspondence relationship between i and an i^th bit value of a second sequence, an (A+m)^th bit value of the second sequence; where i is an integer greater than or equal to 1 and less than or equal to M.

Accordingly, the determination module 303 is specifically configured to: determine, according to the (A+m)^th bit value of the first sequence and the (A+m)^th bit value of the second sequence, an m^th bit value of the pseudo-random sequence.

The specific implementation process of the apparatus for generating a pseudo-random sequence is the same as that of the method for generating a pseudo-random sequence in the foregoing embodiments, and thus is not repeated here.

Those of ordinary skill in the art will appreciate that all or some operations of the above described method, functional modules/units in the system and apparatus may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or operation may be performed cooperatively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a CPU, a digital signal processor or microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium which may include a computer storage medium (or non-transitory medium) and communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and nonvolatile, removable and non-removable medium implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules or other data. The computer storage medium includes, but is not limited to, an RAM, an ROM, an EEPROM, a flash or any other memory technology, a CD-ROM, a digital versatile disc (DVD) or any other optical disc storage, a magnetic cartridge, a magnetic tape, a magnetic disk storage or any other magnetic memories, or may be any other medium used for storing the desired information and accessible by a computer. Moreover, it is well known to those ordinary skilled in the art that a communication medium typically includes a computer-readable instruction, a data structure, a program module, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and may include any information delivery medium.

The present disclosure has disclosed exemplary embodiments, and although specific terms are employed, they are used and should be interpreted merely in a generic and descriptive sense, not for purposes of limitation. In some instances, as would be apparent to one skilled in the art, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with another embodiment, unless expressly stated otherwise. It will, therefore, be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present application as set forth in the appended claims.

Claims

1. A method for generating a pseudo-random sequence, comprising: performing an AND operation and an XOR operation on M bit values of a first sequence to obtain an (A+m)th bit value of the first sequence, where M is an integer greater than or equal to 1, and A is an integer greater than or equal to 0; anddetermining, according to the (A+m)th bit value of the first sequence, an mth bit value of the pseudo-random sequence.

2. The method according to claim 1, wherein performing the AND operation and the XOR operation on M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence comprises: performing an AND operation on an ith bit value in the M bit values and k(m.i)to obtain a corresponding ith intermediate bit value, where i is an integer greater than or equal to 1 and less than or equal to M, and k(m.i) is a proportionality coefficient corresponding to the ith bit value and m; where m is an integer greater than or equal to 0; andperforming an XOR operation on M intermediate bit values to obtain the (A+m)th bit value of the first sequence.

3. The method according to claim 2, wherein before performing the AND operation on the ith bit value in the M bit values and k(m.i) to obtain the corresponding ith intermediate bit value, the method further comprises: determining k(m.i) according to a first correspondence relationship among i, m and k(m.i).

4. The method according to claim 1, wherein the AND operation and the XOR operation corresponding to m of a same segment are performed in parallel, and determination of bit values belonging to a same segment in the pseudo-random sequence is performed in parallel, wherein each segment comprises N bit values of the pseudo-random sequence, where N is an integer greater than or equal to 2; and the segment is obtained by dividing the pseudo-random sequence.

5. The method according to claim 4, wherein N is less than or equal to a maximum parallel number supported by a processor.

6. The method according to claim 1, wherein M is less than or equal to a bit width of a processor.

7. The method according to claim 1, wherein the M bit values comprise: a jth bit value to a (j+M-1)th bit value, where j is an integer greater than or equal to 0.

8. The method according to claim 1, wherein performing the AND operation and the XOR operation on M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence, the method further comprises: calculating, according to an initial value of the first sequence, M bit values of the first sequence.

9. The method according to claim 1, wherein before determining, according to the (A+m)th bit value of the first sequence, the mth bit value of the pseudo-random sequence, the method further comprises: acquiring, according to a preset second correspondence relationship between i and an ith bit value of a second sequence, an (A+m)th bit value of the second sequence, where i is an integer greater than or equal to 1 and less than or equal to M; accordingly, determining, according to the (A+m)th bit value of the first sequence, the mth bit value of the pseudo-random sequence comprises: determining, according to the (A+m)th bit value of the first sequence and the (A+m)th bit value of the second sequence, the mth bit value of the pseudo-random sequence.

10. An electronic device, comprising: at least one processor; anda memory having at least one program stored thereon which, when executed by the at least one processor, causes the at least one processor to implement the method for generating a pseudo-random sequence according claim 1.

11. A computer readable storage medium having a computer program stored thereon which, when executed by a processor, causes the method for generating a pseudo-random sequence according to claim 1 to be implemented.

12. An apparatus for generating a pseudo-random sequence, comprising: a calculation module configured to calculate, according to an initial value of a first sequence, M bit values of the first sequence, where M is an integer greater than or equal to 1;a logic operation module configured to perform an AND operation and an XOR operation on the M bit values to obtain an (A+m)th bit value of the first sequence, where A is an integer greater than or equal to 0; anda determination module configured to determine, according to the (A+m)th bit value of the first sequence, an mth bit value of the pseudo-random sequence.

13. The method according to claim 2, wherein the AND operation and the XOR operation corresponding to m of a same segment are performed in parallel, and determination of bit values belonging to a same segment in the pseudo-random sequence is performed in parallel, wherein each segment comprises N bit values of the pseudo-random sequence, where N is an integer greater than or equal to 2; and the segment is obtained by dividing the pseudo-random sequence.

14. The method according to claim 3, wherein the AND operation and the XOR operation corresponding to m of a same segment are performed in parallel, and determination of bit values belonging to a same segment in the pseudo-random sequence is performed in parallel, wherein each segment comprises N bit values of the pseudo-random sequence, where N is an integer greater than or equal to 2; and the segment is obtained by dividing the pseudo-random sequence.

15. The method according to claim 2, wherein performing the AND operation and the XOR operation on M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence, the method further comprises: calculating, according to an initial value of the first sequence, M bit values of the first sequence.

16. The method according to claim 3, wherein performing the AND operation and the XOR operation on M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence, the method further comprises: calculating, according to an initial value of the first sequence, M bit values of the first sequence.

17. The method according to claim 2, wherein before determining, according to the (A+m)th bit value of the first sequence, the mth bit value of the pseudo-random sequence, the method further comprises: acquiring, according to a preset second correspondence relationship between i and an ith bit value of a second sequence, an (A+m)th bit value of the second sequence, where i is an integer greater than or equal to 1 and less than or equal to M; accordingly, determining, according to the (A+m)th bit value of the first sequence, the mth bit value of the pseudo-random sequence comprises: determining, according to the (A+m)th bit value of the first sequence and the (A+m)th bit value of the second sequence, the mth bit value of the pseudo-random sequence.

18. The method according to claim 3, wherein before determining, according to the (A+m)th bit value of the first sequence, the mth bit value of the pseudo-random sequence, the method further comprises: acquiring, according to a preset second correspondence relationship between i and an ith bit value of a second sequence, an (A+m)th bit value of the second sequence, where i is an integer greater than or equal to 1 and less than or equal to M; accordingly, determining, according to the (A+m)th bit value of the first sequence, the mth bit value of the pseudo-random sequence comprises: determining, according to the (A+m)th bit value of the first sequence and the (A+m)th bit value of the second sequence, the mth bit value of the pseudo-random sequence.

19. The method according to claim 4, wherein before determining, according to the (A+m)th bit value of the first sequence, the mth bit value of the pseudo-random sequence, the method further comprises: acquiring, according to a preset second correspondence relationship between i and an ith bit value of a second sequence, an (A+m)th bit value of the second sequence, where i is an integer greater than or equal to 1 and less than or equal to M; accordingly, determining, according to the (A+m)th bit value of the first sequence, the mth bit value of the pseudo-random sequence comprises: determining, according to the (A+m)th bit value of the first sequence and the (A+m)th bit value of the second sequence, the mth bit value of the pseudo-random sequence.

20. The method according to claim 5, wherein before determining, according to the (A+m)th bit value of the first sequence, the mth bit value of the pseudo-random sequence, the method further comprises: acquiring, according to a preset second correspondence relationship between i and an ith bit value of a second sequence, an (A+m)th bit value of the second sequence, where i is an integer greater than or equal to 1 and less than or equal to M; accordingly, determining, according to the (A+m)th bit value of the first sequence, the mth bit value of the pseudo-random sequence comprises: determining, according to the (A+m)th bit value of the first sequence and the (A+m)th bit value of the second sequence, the mth bit value of the pseudo-random sequence.