1. Field of the Invention
This invention relates to methods to self-synchronize clocks on multiple chips in a system.
2. Description of Background
In a synchronous digital system comprised of multiple chips with synchronous communications among them, cross-chip functions often require a synchronized “time-zero” over a certain predefined number of clock cycles. To properly synchronize the time-zero of all the chips in the same system, a method is required to synchronize the counters that keep track of the “time-zero” on all the chips. One way to accomplish this is through the methods described in patent application Ser. No. 11/056,767, Methods to Self-synchronize Clocks on Multiple Chips in a System. All of the synchronization methods described therein rely on a synchronization signal generated off of the input reference clock and a PLL-generated global clock of the chip. This is as shown in the example in
The generation of the synchronization signal from the reference clock and chip global clock may be done with edge detection logic at a slower frequency. In high performance server system designs desk with multiple chips, a common practice for server systems is to use a feedback clock, clkfbk 17, and a delayed reference clock, clkrefd 18, to generate the synchronization signal as shown in
A synchronization signal generation circuit 24 is clocked by feedback clock, clkfbk 17. The generated synchronization signal 15 has to be eventually transferred to latches clocked by the global clock, clkg 13, to be used for chip synchronization functions. The phase mismatch of feedback clock, clkfbk 17, and clkg 13 is equal to the delay of mimic receiver 33, mimic logic circuitry 35, and mimic local clock buffer 37 (dr+dl+db). When the clock cycle time is long compared to td=dr+dl+db, this extra delay is not a concern for transferring a synchronization signal 15 to a first latch (latch 1) 38 (
In current generation high performance systems, this phase mismatch approaches the chip cycle time, so the synchronization signal 15 cannot be properly transferred from the synchronization signal generation circuit 24 clocked by the feedback clock 17 to the chip logic running on chip global clock 13 without uncertainty.
As shown in
This invention resolves the uncertainty problem and allows the synchronization signals to be generated deterministically independent of the chip global clock cycle time.
Embodiment I
Referring to
Embodiment II
When td is more than 1.5 times the minimum global clock cycle time, even the approach used by embodiment I is not adequate to receive the synchronization signal at the second latch 40, clocked by clkg 13, without uncertainty. Because if the chip could run at a slower frequency than the maximum frequency, the cycle relative to clkg 13 in which the synchronization signal is latched may be uncertain as the chip slows down and the mimic circuitry delay, td, is close to an integral multiple of a slowed down clkg cycle time. The solution proposed (as shown, for example, in
a) Intentionally place the mimic receiver 33 and the mimic local clock buffer 37 at the beginning of the feedback path.
b) Use the delayed global clock cld from the output of the mimic receiver 33/local clock buffer 37 combination and the reference clock clkrefd0 from the output of the receiver 21 to generate the synchronization signal 15.
b) Use the delayed clkg 13 from the output of mimic receiver 33/local clock buffer 37 combination and the reference clock from the output of the receiver to generate the synchronization signal.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.
As a result of the summarized invention, technically we have achieved a solution which resolves clock signal uncertainty and facilitates the synchronization signals being generated deterministically independent of the chip global clock cycle time.
The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
a and 5b illustrate examples of two synchronization signal generation circuits clocked by an inverted feedback clock with optional combination logic.
The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.
Embodiment I
Referring to
Other variations to this scheme include using the inverted feedback clock 117 to clock the synchronization signal generation circuit 24 as shown in
Embodiment II
When, td is more than 1.5 times of the minimum global clock cycle time, even the approach used by embodiment I is not adequate to receive the synchronization signal at the second latch 40, clocked by clkg 13, without uncertainty. When the chip runs at a slower frequency than the maximum frequency, the cycle relative to clkg 13 in which the synchronization signal is latched at latch 2 may become uncertain if the mimic circuitry delay, td, is close to an integral multiple of a slowed down clkg cycle time as shown in
To make the design frequency independent, we'll need to generate the synchronization signal with two other clock sources that do not have large phase misalignment with the global clock, clkg. An ideal source will be the reference clock clkrefd0 (
The phase mismatch between cld and clkg, dr+db, in general is usually small compared to clkg cycle time. To further reduce the mismatch, one can use cld to launch the synchronization signal 15 from the synchronization signal generation circuit 24 and add local clock buffers 42 for latches 38, 40 at downstream locations as shown in
This embodiment can further be combined with embodiment I. If the remaining phase mismatch, dr, ever becomes a large portion of the clkg cycle time, one may use the technique described in embodiment I to gain half of clkg cycle for the path between the synchronization signal generation circuit 24 and latch 1 as shown in
To implement the scheme described in embodiment II, mimic receiver 33 should be placed near the reference clock receiver 21 to minimize the extra phase difference of the two input clocks to synchronization signal generation circuit 24 resulting from unwanted long routing. This is in general feasible because the reference clock chip input pins and receiver are placed close to the target PLL 25. In case this is not easy to achieve at chip floorplanning, a more universal way is to use a local clock buffer 29 that is driven by clkg and feed the output, cl , to a mimic receiver 33a as shown in
The synchronization signal generation circuit 24 can be an edge detection circuit. One example is shown in
In the example shown in
In systems that may have concerns with transient clock jitter of clkg that causes large phase mismatch between clkrefd0 and clkg, which may result in a synchronization signal being temporarily incorrectly generated, one solution is to use a counter controlled by the generated synchronization signal during start up. After the startup period, the counter may be left free running
The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof.
As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately.
Additionally, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided.
The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
This application is a divisional of and claims priority to U.S. Non-provisional application Ser. No. 11/363,871, entitled “METHOD AND APPARATUS FOR GENERATING SYNCHRONIZATION SIGNALS FOR SYNCHRONIZING MULTIPLE CHIPS IN A SYSTEM”, filed Feb. 28, 2006, now U.S. Pat. No. 7,826,579, which is a continuation in part of U.S. Non-provisional application Ser. No. 11/056,767, entitled “METHODS TO SELF-SYNCHRONIZE CLOCKS ON MULTIPLE CHIPS IN A SYSTEM” filed Feb. 11, 2005, now U.S. Pat. No. 7,382,844, both of which applications are hereby incorporated herein by reference in their entirety.
Number | Name | Date | Kind |
---|---|---|---|
5850414 | Miyajima | Dec 1998 | A |
5995570 | Onvural et al. | Nov 1999 | A |
6470458 | Dreps et al. | Oct 2002 | B1 |
6665359 | Flake | Dec 2003 | B1 |
6751248 | Tan | Jun 2004 | B1 |
6792554 | Gervais et al. | Sep 2004 | B2 |
6819726 | Drerup et al. | Nov 2004 | B2 |
7065168 | Dedic et al. | Jun 2006 | B2 |
7098707 | Starr et al. | Aug 2006 | B2 |
7174475 | Lee et al. | Feb 2007 | B2 |
20030091137 | Vallet et al. | May 2003 | A1 |
Number | Date | Country | |
---|---|---|---|
20110033017 A1 | Feb 2011 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 11363871 | Feb 2006 | US |
Child | 12906658 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 11056767 | Feb 2005 | US |
Child | 11363871 | US |