Patent Application
20090150750
This disclosure relates generally to apparatus and methods for encoding. More particularly, the disclosure relates to hybrid automatic repeat request (HARQ) encoding scheme with low memory requirement.
Wireless communication systems are widely deployed to provide various types of communication content such as voice, data, and so on. These systems may be multiple-access systems capable of supporting communication with multiple users by sharing the available system resources (e.g., bandwidth and transmit power). Examples of such multiple-access systems include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, 3GPP LTE systems, and orthogonal frequency division multiple access (OFDMA) systems.
Generally, a wireless multiple-access communication system can simultaneously support communication for multiple wireless terminals. Each terminal communicates with one or more base stations via transmissions on the forward and reverse links. The forward link (or downlink) refers to the communication link from the base stations to the terminals (e.g., a mobile station), and the reverse link (or uplink) refers to the communication link from the terminals to the base stations. This communication link may be established via a single input-single output, multiple input-single output or a multiple-input-multiple-output (MIMO) system.
A MIMO system employs multiple (NT) transmit antennas and multiple (NR) receive antennas for data transmission. A MIMO channel formed by the NT transmit and NR receive antennas may be decomposed into NS independent channels, which are also referred to as spatial channels, where NS≦min{NT, NR}. Each of the NS independent channels corresponds to a dimension. The MIMO system can provide improved performance (e.g., higher throughput and/or greater reliability) if the additional dimensionalities created by the multiple transmit and receive antennas are utilized. For example, a MIMO system can support time division duplex (TDD) and frequency division duplex (FDD) systems. In a TDD system, the forward and reverse link transmissions are on the same frequency region so that the reciprocity principle allows the estimation of the forward link channel from the reverse link channel. This enables the access point to extract transmit beamforming gain on the forward link when multiple antennas are available at the access point.
Wireless communication systems are subject to various channel perturbations and noise disturbances which are introduced somewhere in the wireless link. These imperfections result in errors in the data processed by a receiver. In general, there are two broad categories of error control applicable to wireless communication systems, error detection and error correction. Error detection techniques, such as automatic repeat request (ARQ), typically add a few redundant bits to a transmit data frame for the purpose of error detection. If an error is detected, the receiver typically sends back an error detection message to the transmitter to request a retransmission of the same transmit data frame. In contrast, error correction techniques, such as forward error correction (FEC), typically add more redundant bits in a structured manner to a transmit data frame for the purpose of error correction. Error correction allows the receiver to both detect and correct received errors, without feedback and retransmission. Depending on the channel error characteristics and throughput versus latency requirements on the system, error detection or error correction might be preferred.
Disclosed is an apparatus and method for HARQ encoding scheme with low memory requirement. According to one aspect, a method for hybrid automatic repeat request (HARQ) encoding comprising re-encoding a subpacket from a plurality of subpackets to obtain a codeword; maintaining a set of state variables for each of the plurality of subpackets; initializing the set of state variables at HARQ transmit start; updating the set of state variables at HARQ transmit end; and using the set of updated state variables to determine a portion of the codeword to be transmitted.
According to another aspect, a transmit data processor for hybrid automatic repeat request (HARQ) encoding comprising a channel encoder module configured to: a) re-encode a subpacket from a plurality of subpackets to obtain a codeword; b) maintain a set of state variables for each of the plurality of subpackets; c) initialize the set of state variables at HARQ transmit start; and d) update the set of state variables at HARQ transmit end; and a multiplexer module configured to use the set of updated state variables to determine a portion of the codeword to be transmitted.
According to another aspect, an apparatus for hybrid automatic repeat request (HARQ) encoding comprising means for re-encoding a subpacket from a plurality of subpackets to obtain a codeword; means for maintaining a set of state variables for each of the plurality of subpackets; means for initializing the set of state variables at HARQ transmit start; means for updating the set of state variables at HARQ transmit end; and means for using the set of updated state variables to determine a portion of the codeword to be transmitted.
According to another aspect, a computer-readable medium including program code stored thereon, comprising program code for re-encoding a subpacket from a plurality of subpackets to obtain a codeword; program code for maintaining a set of state variables for each of the plurality of subpackets; program code for initializing the set of state variables at HARQ transmit start; program code for updating the set of state variables at HARQ transmit end; and program code for using the set of updated state variables to determine a portion of the codeword to be transmitted.
Advantages of the present disclosure include reducing chip memory without increasing peak processor speed budget. In one example, the memory saving is approximately five times that of conventional approach.
It is understood that other aspects will become readily apparent to those skilled in the art from the following detailed description, wherein it is shown and described various aspects by way of illustration. The drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.
a and 5b illustrate examples of MAC packet descriptor for immediate and indirect cases, respectively.
The detailed description set forth below in connection with the appended drawings is intended as a description of various aspects of the present disclosure and is not intended to represent the only aspects in which the present disclosure may be practiced. Each aspect described in this disclosure is provided merely as an example or illustration of the present disclosure, and should not necessarily be construed as preferred or advantageous over other aspects. The detailed description includes specific details for the purpose of providing a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the present disclosure. Acronyms and other descriptive terminology may be used merely for convenience and clarity and are not intended to limit the scope of the disclosure.
While for purposes of simplicity of explanation, the methodologies are shown and described as a series of acts, it is to be understood and appreciated that the methodologies are not limited by the order of acts, as some acts may, in accordance with one or more aspects, occur in different orders and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all illustrated acts may be required to implement a methodology in accordance with one or more aspects.
The techniques described herein may be used for various wireless communication systems such as Code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Frequency Division Multiple Access (FDMA) systems, Orthogonal FDMA (OFDMA) systems, Single-Carrier FDMA (SC-FDMA) systems, etc. The terms “systems” and “networks” are often used interchangeably. A CDMA system may implement a radio technology such as Universal Terrestrial Radio Access (UTRA), cdma2000, etc. UTRA includes Wideband-CDMA (W-CDMA) and Low Chip Rate (LCR). Cdma2000 covers IS-2000, IS-95 and IS-856 standards. A TDMA system may implement a radio technology such as Global System for Mobile Communications (GSM). An OFDMA system may implement a radio technology such as Evolved UTRA (E-UTRA), IEEE 802.11, IEEE 802.16, IEEE 802.20, Flash-OFDM®, etc. UTRA, E-UTRA, and GSM are part of Universal Mobile Telecommunication System (UMTS). Long Term Evolution (LTE) is an upcoming release of UMTS that uses E-UTRA. UTRA, E-UTRA, GSM, UMTS and LTE are described in documents from an organization named “3rd Generation Partnership Project” (3GPP). Cdma2000 is described in documents from an organization named “3rd Generation Partnership Project 2” (3GPP2). These various radio technologies and standards are known in the art.
Additionally, single carrier frequency division multiple access (SC-FDMA), which utilizes single carrier modulation and frequency domain equalization is another wireless communication technique. A SC-FDMA system can have similar performance and the same overall complexity as those of an OFDMA system. SC-FDMA signal has lower peak-to-average power ratio (PAPR) because of its inherent single carrier structure. SC-FDMA has drawn great attention, especially in uplink communications where lower PAPR greatly benefits the mobile terminal in terms of transmit power efficiency. Using SC-FDMA technique is currently a working assumption for uplink multiple access scheme in 3GPP Long Term Evolution (LTE), or Evolved UTRA. All of the above wireless communication techniques and standards may be used with the data centric multiplexing algorithms described herein.
In communication over forward links 120 and 126, the transmitting antennas of access point 100 utilize beamforming in order to improve the signal-to-noise ratio of forward links for the different access terminals 116 and 124. Also, an access point using beamforming to transmit to access terminals scattered randomly through its coverage causes less interference to access terminals in neighboring cells than an access point transmitting through a single antenna to all its access terminals. An access point may be a fixed station. An access point may also be referred to as an access node, a base station or some other similar terminology known in the art. An access terminal may also be called a mobile station, a user equipment (UE), a wireless communication device or some other similar terminology known in the art.
The coded data for each data stream may be multiplexed with pilot data using OFDM techniques. The pilot data is typically a known data pattern that is processed in a known manner and may be used at the receiver system to estimate the channel response. The multiplexed pilot and coded data for each data stream is then modulated (i.e., symbol mapped) based on a particular modulation scheme (e.g., BPSK, QSPK, M-PSK, or M-QAM) selected for that data stream to provide modulation symbols. The data rate, coding, and modulation for each data stream may be determined by instructions performed by processor 230.
The modulation symbols for all data streams are then provided to a TX MIMO processor 220, which may further process the modulation symbols (e.g., for OFDM). TX MIMO processor 220 then provides NT modulation symbol streams to NT transmitters (TMTR) 222a through 222t. In one example, the TX MIMO processor 220 applies beamforming weights to the symbols of the data streams and to the antenna from which the symbol is being transmitted. Each transmitter 222a, or, 222t receives and processes a respective symbol stream to provide one or more analog signals, and further conditions (e.g., amplifies, filters, and upconverts) the analog signals to provide a modulated signal suitable for transmission over the MIMO channel. NT modulated signals from transmitters 222a through 222t are then transmitted from NT antennas 224a through 224t, respectively.
At receiver system 250, the transmitted modulated signals are received by NR antennas 252a through 252r and the received signal from each antenna 252a, or 252r is provided to a respective receiver (RCVR) 254a through 254r. Each receiver 254 a, . . . or 254r conditions (e.g., filters, amplifies, and downconverts) a respective received signal, digitizes the conditioned signal to provide samples, and further processes the samples to provide a corresponding “received” symbol stream.
A RX data processor 260 then receives and processes the NR received symbol streams from NR receivers 254a through 254r based on a particular receiver processing technique to provide NT “detected” symbol streams. The RX data processor 260 then demodulates, deinterleaves, and decodes each detected symbol stream to recover the traffic data for the data stream. The processing by RX data processor 260 is complementary to that performed by TX MIMO processor 220 and TX data processor 214 at transmitter system 210. A processor 270 periodically determines which pre-coding matrix to use (discussed below). Processor 270 formulates a reverse link message comprising a matrix index portion and a rank value portion.
The reverse link message may comprise various types of information regarding the communication link and/or the received data stream. The reverse link message is then processed by a TX data processor 238, which also receives traffic data for a number of data streams from a data source 236, modulated by a modulator 280, conditioned by transmitters 254a through 254r, and transmitted back to transmitter system 210.
At transmitter system 210, the modulated signals from receiver system 250 are received by antennas 224a through 224t, conditioned by receivers 222a through 222t, demodulated by a demodulator 240, and processed by a RX data processor 242 to extract the reserve link message transmitted by the receiver system 250. Processor 230 then determines which pre-coding matrix to use for determining the beamforming weights, then the processor 230 processes the extracted message. One skilled in the art would understand that the transceivers 222a through 222t are called transmitters in the forward link and receivers in the reverse link. Similarly, one skilled in the art would understand that the transceivers 254a through 254r are called receivers in the forward link and transmitters in the reverse link.
As stated above, depending on the channel error characteristics and throughput versus latency requirements on the system, error detection or error correction might be preferred. Hybrid ARQ (HARQ) is a third error control category which combines features of both error detection and error correction in an attempt to attain the benefits of both techniques. In one example of HARQ, the first transmission of a transmit data frame may contain only error detection bits. If the receiver determines that the data frame is received without error, no retransmission is requested. However, if the receiver determines that the data frame is received in error, using the error detection bits, then an error detection message is sent back to the transmitter, which sends a second transmission of the transmit data frame along with additional error correction bits. Then, if the receiver determines that the data frame is again received in error, beyond the capability of the additional error correction bits, another error detection message is sent back to the transmitter, which sends a third transmission of the transmit data frame along with a separate set of error correction bits. In general, HARQ retransmissions may be repeated for the same transmit data frame until it is received without error or up to a predetermined maximum number of retransmissions, whichever occurs first.
In one example, in a Ultra Mobile Broadband (UMB) system for the Forward Link Data Channel (FLDCH), the incoming Media Access Control (MAC) packets are first split into subpackets, whose length is less than or equal to, for example, 4 kbits. Then the subpackets are fed into a turbo/convolutional encoder to be encoded, interleaved and repeated. The output bit stream for each subpacket, called the codeword, could be, for example, 5 times longer than the subpacket, due to the forward error correction overhead. The codeword is then transmitted across multiple HARQ transmissions with repetition if necessary. The HARQ transmissions are in general separated by a length of time. For instance, in HARQ8, the codeword is transmitted once every 8 frames. For each transmitted frame, only partial bits of the entire codeword are transmitted. In the conventional design, the entire encoded codeword is stored in memory. The total memory required will be at least 5 times the sum of length of all incoming MAC packets. For example in the forward link of UMB, assuming worst case numbers (i.e. highest packet format for all the tiles (128)) 4 layers and an HARQ interlace depth of 8 frames, the conventional design requires around 25 Mbit on-chip memory.
The input L2 module 410 generates the RLP headers, RLP data, and the crypto stream. The information generated by the input L2 module 410 enables the MAC packet assembler and encryptor 420 to assemble the subpacket. The MAC packet descriptor is illustrated in
In one example, the transmit data processor of
In one aspect, the required on-chip memory is drastically reduces to, for example, less than 1 Mbit. Referring back to
The maintenance of state variables by the channel encoder module 320 and/or by the multiplexer module 330 simplifies the design of the channel encoder module 320 because it does not require knowledge of any other channels which overlap with the DCH resource (e.g. channel quality indicator (CQI), beacon, etc). The channel encoder module 320 is always working on assignments scheduled for the next frame, while the multiplexer module 330 is working on the current frame. In the case when an assignment spreads across contiguous frames (extended or elongated frames) the channel encoder module 320 will not have up-to-date state variable information from the multiplexer module 330. In this case, the channel encoder module 320 just assumes some worst case values for the state variables and provides some extra bits for each subpacket 312. By the time the multiplexer module 330 gets to the next frame, the state variables will be updated and used to select only the appropriate bits.
One skilled in the art would understand that the steps disclosed in the example flow diagram in
Those of skill would further appreciate that the various illustrative components, logical blocks, modules, circuits, and/or algorithm steps described in connection with the examples disclosed herein may be implemented as electronic hardware, firmware, computer software, or combinations thereof. To clearly illustrate this interchangeability of hardware, firmware and software, various illustrative components, blocks, modules, circuits, and/or algorithm steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware, firmware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope or spirit of the present disclosure.
For example, for a hardware implementation, the processing units may be implemented within one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described therein, or a combination thereof. With software, the implementation may be through modules (e.g., procedures, functions, etc.) that perform the functions described therein. The software codes may be stored in memory units and executed by a processor unit. Additionally, the various illustrative flow diagrams, logical blocks, modules and/or algorithm steps described herein may also be coded as computer-readable instructions carried on any computer-readable medium known in the art or implemented in any computer program product known in the art.
In one example, the illustrative components, flow diagrams, logical blocks, modules and/or algorithm steps described herein are implemented or performed with one or more processors. In one aspect, a processor is coupled with a memory which stores data, metadata, program instructions, etc. to be executed by the processor for implementing or performing the various flow diagrams, logical blocks and/or modules described herein.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the spirit or scope of the disclosure.
The present application for patent claims priority to Provisional Application No. 60/992,433, entitled HARQ Encoding Scheme With Low Memory Requirement filed on Dec. 5, 2007, and assigned to the assignee hereof and hereby expressly incorporated by reference herein.
| Number | Date | Country | |
|---|---|---|---|
| 60992433 | Dec 2007 | US |
