Patent Application
20080043148
These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
The frequency of the intermediate clock signal is equal to the frequency of the output clock signal multiplied by the ratio of the input horizontal resolution to the output horizontal resolution, represented as:
For example, the resolution of the source image is 720×240, and the resolution of the output image is 640×480. In step 202, the source image is received using the input clock signal with a frequency of 13.5 MHz, which is determined by the resolution of the source image. In step 204, the received source image scales up the vertical resolution from 240 lines to 480 lines while the horizontal resolution thereof remains unchanged, and thus the intermediate image with a 720×480 resolution is generated using the intermediate clock signal with a frequency of 28.35 MHz. In step 206, the intermediate image scales down the horizontal resolution from 720 pixels to 640 pixels while the vertical resolution thereof remains unchanged, and therefore the output image is generated using the output clock signal with a frequency of 25.2 MHz.
In the preferred embodiment, the source image and the output image can have the same or different aspect ratios, and the scaling steps can selectively scale up or scale down the images. Moreover, the intermediate clock signal and the output clock signal can both be generated by a phase-locked loop, which is modified to have two frequency dividers for outputting clock signals with different frequencies, respectively. More particularly, a ratio of the factors of the two frequency dividers is equal to the ratio the input horizontal resolution to the output horizontal resolution as mentioned above. Therefore, the preferred embodiment can have both of the required clock signals with only one modified phase-locked loop, saving the occupied area thereof.
The first frequency divider 312 outputs the intermediate clock signal for generating the intermediate image, and the second frequency divider 314 outputs the output clock signal for generating the output image. The frequency of the intermediate clock signal is equal to the frequency of the output clock signal multiplied by the ratio of an input horizontal resolution of the source image to an output horizontal resolution of the output image. More precisely, the ratio of the factors of the two frequency dividers 312 and 314 is equal to the ratio of the input horizontal resolution to the output horizontal resolution
In other words, the preferred embodiment can also provide an image scaler, which uses a modified phase-locked loop instead of two conventional phase-locked loops. The image scaler is characterized by comprising the modified phase-locked loop 300, which has two frequency dividers 312 and 314 IS for outputting the intermediate clock signal and the output clock signal, respectively, and the frequency of the intermediate clock signal is equal to the frequency of the output clock signal multiplied by the ratio of the input horizontal resolution to the output horizontal resolution.
The following describes the comparison of minimal memory buffer size between the first conventional image scaler, the second conventional image scaler and the image scaler of the preferred embodiment as mentioned above. For the three image scalers, the resolution of the source image is 720×240, the resolution of the intermediate image is 720×480, and the resolution of the output image is 640×480.
The frequency of the input clock signal is 13.5 MHz, the frequency of the output clock signal is 25.2 MHz, and the frequency of the intermediate clock signal is 27 MHz.
Time for horizontal pixel buffer write is 720×(1/27M)=26666 ns.
Time for horizontal pixel buffer read is 640×(1/25.2M)=25396 ns.
The minimal horizontal pixel buffer size is (26666−25396)×27=47 pixels.
The frequency of the input clock signal is 13.5 MHz, the frequency of the output clock signal is 25.2 MHz, and the frequency of the intermediate clock signal is 25.2 MHz.
Time for horizontal pixel buffer write is 720×(1/25.2M)=28571 ns.
Time for horizontal pixel buffer read is 640×(1/25.2M)=25396 ns.
The minimal horizontal pixel buffer size is (28571−25396)×25.2=80 pixels.
The frequency of the input clock signal is 13.5 MHz, the frequency of the output clock signal is 25.2 MHz, and the frequency of the intermediate clock signal is 25.2×(720/640)=28.35 MHz.
Time for horizontal pixel buffer write is 720×(1/28.35M)=25396 ns.
Time for horizontal pixel buffer read is 640×(1/25.2M)=25396 ns.
The minimal horizontal pixel buffer size is (25396−25396)×28.35=0 pixels.
Accordingly, the preferred embodiment theoretically can make the size of the horizontal pixel buffer approach zero, substantially decreasing the occupied area of a memory buffer. However, in practice, some spare bits of the memory buffer still can be reserved for accidental data waiting.
In conclusion, the preferred embodiment can provide a phase-lock loop used in an image scaler and the method thereof, which especially determines the frequency of the intermediate clock signal by the relationship of the input horizontal resolution and the output horizontal resolution, to reduce the size of the horizontal pixel buffer. By this architecture, the chip size of the image scaler can be decreased, and only one modified phase-locked loop is required to complete the image scaling.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
