Method and apparatus for implementing DC mode selection in a data access arrangement

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of data communication equipment, and in particular to artificial inductors in data access arrangements.
2. Background Art
Telephone systems were originally designed for simple voice communication. As new technologies have emerged, methods have been devised to provide more advanced voice communication functions, as well as to transmit other types of information over telephone lines. These methods typically require the connection of electronic equipment, other than the voice telephone set, to the telephone line. Examples of such equipment include computer modems, facsimile ("fax") machines, answering machines, voice mail systems, phone patches, automatic number identification (ANI) or "Caller ID" systems, and advanced telephone systems.
The electrical characteristics of signals present within the above equipment often differ from the electrical characteristics permitted on a standard twisted-pair telephone line used to connect the equipment to a central office (CO) of the local telephone service provider. An interface circuit referred to as a data access arrangement (DAA) is utilized to couple the equipment to the telephone line. The data access arrangement typically provides isolation, impedance matching, and sometimes amplification, filtering and control functions.
Unfortunately, the specifications for data access arrangements may differ from region to region or country to country to meet the electrical operating parameters of the respective central office. Therefore, a particular data access arrangement has utility only in those countries where the operating specifications are met. The relationship between the data access arrangement and the central office is more clearly understood with reference to a sample data access arrangement as illustrated in FIG. 1.
DATA ACCESS ARRANGEMENT CIRCUIT
FIG. 1 is simplified circuit diagram of a data access arrangement. Transmit (TX) and receive (RX) signal lines are provided on the user side of the circuit for coupling to a modem or other equipment. "Tip" and "ring" lines are provided for coupling to the twisted-pair telephone line on the central office side.
In FIG. 1, the transmit signal (TX) 100 is provided to amplifier 102 of the data access arrangement circuit. The output of amplifier 102 is coupled via impedance 104 to node 105. Receive signal (RX) 101 is extracted from node 105 via amplifier 103. Hybrid transformer 106 comprises a secondary winding coupled between node 105 and a ground voltage or other stable voltage supply node, and a primary winding coupled between node 107 and node 109. Node 107 is coupled to node 121 via capacitor 108. Artificial inductor 110 and protection element 112 are coupled in parallel between nodes 121 and 109. Further coupled between nodes 109 and 121 is a diode bridge comprising diodes 113-116. Ring line 118 is coupled to node 109 via diode 115, and node 121 via diode 116. Tip line 120 is coupled via switch 119 to node 117. Node 117 is coupled to node 109 via diode 113 and node 121 via diode 114.
The tip and ring lines are connected to the central office in the local loop. The diode bridge formed by diodes 113-116 provides for proper operation of the circuit, since the polarity of the tip and ring lines is not known in advance and may differ from site to site.
Protection element 112 provides protection from excessive voltages and typically presents a high impedance to AC and DC signals. One embodiment of protection element 112 may comprise a plurality of Zener diodes. Artificial inductor 110 presents a high impedance to AC signals, but a relatively lower impedance to DC signals. In contrast, capacitor 108 presents a high impedance to DC signals, and a relatively lower impedance to AC signals. Thus, only AC signals pass between the transmit and receive lines and the tip and ring lines via the hybrid transformer. The DC electrical characteristics of the DAA circuit on one side of the hybrid transformer are isolated from those on the other side of the hybrid transformer.
The AC loop is formed from the central office via the tip line through diode 114 (or diode 113 if opposite polarity), capacitor 108, hybrid transformer 106 and diode 115 (or diode 116) to the ring line 118 of the central office. Via hybrid transformer 106, the AC loop also includes node 105. The modem, or local device, can read the AC signal from node 105 via amplifier 103 and receive signal 101, or append an AC signal to node 105 via transmit signal 100 and elements 102 and 104.
The DC operating point for many of the elements in the DAA circuit are set by the DC loop shown in FIG. 2. The DC loop comprises central office 200, diode 114, artificial inductor 110, and diode 115. The AC and DC loops are completed when switch 119, coupling node 117 to tip line 120, is closed, i.e., when the telephone line is considered "off hook".
In simplified form, the central office 200 may be represented by a DC voltage source in series with a large resistance. In FIG. 2, these elements are identified as V.sub.DC,CO and R.sub.CO. With the DC loop completed, a DC current I.sub.DC is driven through artificial inductor 110, and DC voltage V is generated across the artificial inductor. The relationship between the voltage V and current I.sub.DC is referred to as the DC characteristics or "DC mode" of the artificial inductor.
The DC characteristics of the artificial inductor determine the DC characteristics for all elements in the DC loop, including the central office. Typically, to implement standard circuit operation at the central office with any modem or device coupled to the telephone line, the DC characteristics of the artificial inductor are constrained to predetermined parameter ranges. As previously stated, these predetermined parameter ranges may differ from country to country, limiting the application of any single DC mode. The design of the artificial inductor circuit is therefore critical to the utility of the data access arrangement and the associated device (e.g., modem, etc.) with respect to a single location. As these data access arrangements are often used with laptop modems or other portable equipment, utility in international travel (i.e., with respect to use in multiple countries) is also an issue.
ARTIFICIAL INDUCTOR CIRCUITS
To better understand how an artificial inductor establishes a DC mode in the data access arrangement, a simplified artificial inductor circuit of the prior art is shown in FIG. 3. The circuit must behave like an inductor with respect to frequency response, and must provide a well-defined voltage-current relationship at DC.
In FIG. 3, the artificial inductor circuit comprises capacitor CB, resistors R.sub.1, R.sub.2 and R.sub.E, and Darlington transistor pair Q1, consisting of transistors Q1A and Q1B. The collectors of transistors Q1A and Q1B are coupled to node 121. The emitter of transistor Q1A is coupled to the base of transistor Q1B, and the emitter of transistor Q1B is coupled through resistor R.sub.E to node 109. The base of transistor Q1A is coupled to node 300. Resistor R.sub.1 is coupled between node 121 and node 300, and resistor R.sub.2 and capacitor CB are coupled in parallel between node 300 and node 109.
For simplicity, the collectors of transistors Q1A and Q1B are referred to as the collector of transistor pair Q1; the base of transistor Q1A is referred to as the base of transistor pair Q1; and the emitter of transistor Q1B is referred to as the emitter of transistor pair Q1. Conceivably, a single high-current-gain transistor may be used in place of the Darlington transistor pair Q1. The Darlington pair shown in FIG. 3 comprises npn BJT transistors.
The current gain of Darlington transistor pair Q1 is sufficiently large that the base current of transistor Q1A is negligible in the following discussion. Resistors R.sub.1 and R.sub.2 are large enough so as not to present a significant load to the central office. Therefore, when Darlington transistor pair Q1 is conducting, only a relatively negligible amount of the DC current I.sub.DC flows through resistors R.sub.1 and R.sub.2. Typical value ranges for the elements of FIG. 3 are: R.sub.1, R.sub.2 .apprxeq.20 k.OMEGA.-200 k.OMEGA.; R.sub.E <100 .OMEGA.; and CB.apprxeq.0.1 .mu.F-10 .mu.F.
For AC signals, capacitor CB effectively shorts any voltage across resistor R.sub.2, attenuating any AC current in transistor pair Q1. The effective AC resistance of the artificial inductor approaches the relatively large resistance of resistor R.sub.1.
When transistor pair Q1 is not conducting, i.e., when the voltage across resistor R.sub.2 does not exceed 2V.sub.BE (the turn-on base-emitter voltage of transistor pair Q1), the DC mode is determined by resistors R.sub.1 and R.sub.2 as follows (where, for simplicity, R.sub.X also refers to the resistance value of element R.sub.X):
V(I.sub.DC).apprxeq.I.sub.DC (R.sub.1 +R.sub.2) �Equation 1!
For R.sub.1 and R.sub.2 >>R.sub.E, when transistor pair Q1 is conducting, the DC mode is approximately given by: ##EQU1##
FIG. 4A illustrates the DC mode of the circuit of FIG. 3. Curve 400 represents the voltage V vs. current I.sub.DC for the artificial inductor circuit. Line 401 represents the voltage vs. current of the central office based upon the example central office equivalent DC circuit comprising voltage supply V.sub.DC,CO and resistance R.sub.CO.
Curve 400 begins at the origin and rises linearly at a slope equal to approximately R.sub.1 +R.sub.2. This represents the resistance across the artificial inductor prior to transistor pair Q1 turning on. Transistor pair Q1 begins conducting when the voltage V is approximately equal to 2V.sub.BE (1+R.sub.1 /R.sub.2), and the current I.sub.DC is approximately equal to 2V.sub.BE /R.sub.2. After transistor pair Q1 begins conducting, the slope of curve 400 adjusts to approximately R.sub.E (1+R.sub.1 /R.sub.2).
Line 401 begins with zero current and a voltage of V.sub.DC,CO, which falls linearly with increasing current at a slope of approximately -R.sub.CO. The equation for line 401 is:
V(I.sub.DC).apprxeq.V.sub.DC,CO -R.sub.CO I.sub.DC �Equation 3!
Point 402 represents the intersection of curve 400 and line 401, and thus a stable DC bias point for the DC loop containing the artificial inductor and the central office.
FIG. 4B illustrates a voltage limiting mask used to specify permitted ranges of DC characteristics for data access arrangements in, for instance, European countries. The upper hatched region represents impermissible DC bias points for the DAA circuit. A lower hatched region may also be provided in the mask, setting a lower limit on voltage over a current range.
The DC mode of the artificial inductor must meet the specifications presented by the DC mask of the respective country or region in which the DAA is being utilized. Appropriate resistance values for resistors R.sub.1, R.sub.2 and R.sub.E are chosen such that the particular DC specification mask is satisfied. However, because different countries have different DC masks, the utility of the artificial inductor, and the associated DAA circuit, is limited to use in the country whose mask forms the basis for the selected resistor values. This geographically constrained utility undesirably limits the market for each device. Further, it poses an inconvenience and extra cost for travelers who must purchase separate units to use such circuits in different countries.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for implementing DC mode selection in a data access arrangement (DAA). The present invention overcomes the geographic constraints of the prior art by providing a plurality of selectable DC modes. Each of the selectable DC modes may be designed to meet the DC mask specifications of a desired country or region. The apparatus of the present invention may then be utilized in any of the desired countries or regions by selecting the appropriate DC mode.
To accommodate several possible DC mask parameters, embodiments of the present invention include selection between a plurality of DC mode voltage levels, selection between current limiting and non-current limiting DC modes, and selection between a plurality of current limit values. Control elements, such as opto-couplers controlled by a microcontroller, are used to perform the selection by enabling and disabling circuit elements or connections.
In a first embodiment, a first control element determines the voltage level of the selected DC mode by enabling or disabling a parallel resistance in a voltage divider. A second control element enables or disables current-limiting by enabling or disabling a feedback transistor. A third control element determines the maximum current for current-limited DC modes by altering the gain of a voltage divider circuit in the feedback loop.
In a second embodiment, the number of control elements is minimized while providing a wide range of DC modes. A diode is placed in series with a voltage divider to provide a voltage offset for the chosen DC mode when active. The diode is also in series with the feedback transistor, modifying the turn-on value of the feedback transistor and hence the maximum current of the DC mode. A first control element is used to enable the diode or short the diode as desired. A second control element is used to enable or disable the feedback transistor. Four different DC modes are thus generated. A partitioned resistance arrangement may be used to provide independence between the design of maximum current values and selectable voltage levels.
A further embodiment provides for temperature compensation of the DC current. A thermistor with a negative temperature coefficient compensates for temperature variance in V.sub.BE of the feedback transistor to maintain stable current performance over a range of temperatures. This temperature compensation is of particular benefit in current limiting modes to prevent drift of the maximum current value with temperature.

BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified circuit block diagram of a data access arrangement.
FIG. 2 is a simplified circuit block diagram of the DC loop formed by the data access arrangement and the central office.
FIG. 3 is a simplified circuit diagram of an artificial inductor of the prior art.
FIG. 4A illustrates the DC characteristics of the artificial inductor of FIG. 3 in terms of voltage and current.
FIG. 4B illustrates a voltage limiting DC mask used by some European countries to specify permitted data access arrangement DC characteristics.
FIG. 5 is a simplified circuit diagram of an artificial inductor having two voltage-selectable DC modes.
FIG. 6 illustrates the selectable DC modes for the circuit of FIG. 5 in terms of current.
FIG. 7 illustrates a voltage limiting and current limiting DC mask used by some European countries to specify the DC characteristics permitted for data access arrangements.
FIG. 8 is a simplified circuit diagram of an artificial inductor having selectable current limiting and non-current limiting DC modes.
FIG. 9 illustrates the selectable current limiting DC modes provided by the circuit of FIG. 8.
FIG. 10 is a simplified circuit diagram of a current limited artificial inductor having two selectable maximum current levels.
FIG. 11 illustrates the two selectable current limited DC modes of the circuit of FIG. 10.
FIG. 12 is a circuit diagram of an artificial inductor providing two voltage-selectable DC characteristics, each having a selectable non-current limited mode and two selectable current limited modes.
FIG. 13 illustrates the plurality of selectable DC modes provided by the circuit of FIG. 12.
FIG. 14 is a circuit diagram of an artificial inductor having two control elements for selecting between two voltage levels and current limiting or non-current limiting DC modes.
FIG. 15 illustrates the selectable DC modes provided by the circuit of FIG. 14.
FIG. 16 is a circuit diagram of an artificial inductor having two control elements and temperature compensation circuitry.
FIG. 17 is a plot of transistor base-emitter turn-on voltage versus temperature.
FIG. 18 is a plot of resistance versus temperature for a negative temperature coefficient (NTC) resistor, or thermistor.
FIG. 19 is a plot of a voltage divider function and the base-emitter turn-on voltage versus temperature, wherein the voltage divider contains a resistor and a thermistor.
FIG. 20 is a plot of a voltage divider function and the base-emitter turn-on voltage versus temperature, wherein the voltage divider comprises a thermistor with series and parallel resistance.

DETAILED DESCRIPTION OF THE INVENTION
The present invention is a method and apparatus for implementing DC mode selection in a data access arrangement (DAA). In the following description, numerous specific details are set forth to provide a more thorough description of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well known features have not been described in detail so as not to obscure the present invention.
The present invention allows for selection of a plurality of DC modes to accommodate the varying requirements of DC masks for different countries. Parameters that vary among different countries include (1) voltage level, (2) current limiting or non-current limiting behavior, and (3), for current-limiting countries, maximum current levels. Description is provided below for accomplishing selection of each of these parameters individually. Embodiments of the invention providing selection of all three parameters will then be disclosed.
Selectable Voltage Level in DC Modes
FIG. 5 illustrates an artificial inductor circuit that provides for two selectable DC modes to accommodate two different voltage-limiting masks. Similarly to the circuit of FIG. 3, the collector of transistor pair Q1 is coupled to node 121 and the base is coupled to node 300. The emitter of transistor pair Q1 is coupled via resistor R.sub.E to node 109. Resistor R.sub.1 is coupled between nodes 300 and 121, and resistor R.sub.2 is coupled between nodes 300 and 109. Capacitor CB is coupled between node 300 and 109. Unlike the circuit of FIG. 3, in FIG. 5, resistor R.sub.3 and control element OPTO1 are coupled in series between nodes 300 and 109. Preferably, the values R.sub.1, R.sub.2 and R.sub.2 .vertline..vertline.R.sub.3 are at least ten times the value R.sub.E.
Control element OPTO1 acts as a closed switch when it is on, and as an open switch when it is off. Any sort of transistor or other controllable switching element may be used for this function. However, in DAA circuit applications, opto-couplers are often preferred because they provide galvanic isolation between the DAA circuit and the controller circuitry of the modem or other connected device. Galvanic isolation is important in telephone line circuits because the voltages on the central office side of the hybrid transformer may differ from the voltages in the modem circuit by upwards of fifteen hundred volts due to lightning or coupling of the telephone lines with nearby power lines.
Regardless of the type of control element used, when control element OPTO1 is on, resistor R.sub.3 is effectively coupled in parallel with R.sub.2 and capacitor CB. When control element OPTO1 is off, resistor R.sub.3 is effectively removed from the circuit. Thus, with control element OPTO1 off, the circuit of FIG. 5 behaves similarly to the circuit of FIG. 3.
When the control element OPTO1 is on, resistor R.sub.3 reduces the resistance between node 300 and node 109. This has the effect of reducing the DC resistance prior to transistor pair Q1 turning on, and increasing the effective resistance after Q1 turns on. Further, the voltage V at which Q1 begins conducting is increased due to the modification of the voltage divider formed by resistors R.sub.1 and R.sub.2. The DC mode of the artificial inductor, with transistor pair Q1 conducting and control element OPTO1 on, is defined by: ##EQU2## where ##EQU3##
FIG. 6 illustrates the selectable DC modes of the circuit of FIG. 5. Curve 400 represents the DC mode of circuit of FIG. 5 when control element OPTO1 is off, and is substantially the same as curve 400 from FIG. 4. Curve 600 represents the DC mode of the circuit of FIG. 5 when control element OPTO1 is on. Curve 600 begins at the origin and rises at a slope equivalent approximately to the resistance of resistors R.sub.2 and R.sub.3 in parallel plus the resistance of resistor R.sub.1. With control element OPTO1 turned on, transistor pair Q1 begins conducting when the voltage V is approximately 2V.sub.BE (1+R.sub.1 /(R.sub.2 .vertline..vertline.R.sub.3)) and the current I.sub.DC is approximately 2V.sub.BE /(R.sub.2 .vertline..vertline.R.sub.3). After transistor pair Q1 begins conducting, curve 600 rises at a slope of approximately R.sub.E (1+R.sub.1 /(R.sub.2 .vertline..vertline.R.sub.3))
By selecting appropriate values for resistors R.sub.E, R.sub.1, R.sub.2, and R.sub.3, curves 400 and 600 can be designed to accommodate two different DC mask specifications. The appropriate DC mode can then be selected by turning control element OPTO1 on or off.
II. Selectable Mode for Current Limiting
In some countries, the DC mask includes a current limiting aspect. Such a mask is illustrated in FIG. 7. The mask of FIG. 7 includes an upper voltage limiting region and a separate current limited region. For a small current range below a maximum current I.sub.MAX, the voltage is unlimited. To accommodate countries having such a current limited DC mask, the artificial inductor circuit must be equipped with current limiting circuitry. Such an artificial inductor is illustrated in FIG. 8.
In FIG. 8, the collector of Darlington transistor pair Q1 is coupled to node 121, and the base is coupled to node 300. The emitter of Darlington transistor pair Q1 is coupled via resistor R.sub.E to node 109. Resistor R.sub.1 is coupled between node 121 and node 300. Capacitor CB and resistor R.sub.2 are coupled in parallel between node 300 and node 109. The collector of npn BJT transistor Q2 is coupled to node 300, and the emitter is coupled to node 109. The base of transistor Q2 is coupled to node 800. Resistor R.sub.6 is coupled between the emitter of transistor pair Q1 and node 800. Control element OPTO2 is coupled between node 800 and node 109.
The current limiting circuitry of FIG. 8 comprises control element OPTO2 and resistor R.sub.6. Resistor R.sub.6 is provided to isolate the base of transistor Q2 from the emitter of transistor pair Q1 and resistor R.sub.E. Resistor R.sub.6 is large with respect to resistor R.sub.E. With control element OPTO2 turned on, resistor R6 is effectively coupled in parallel with resistor R.sub.E. However, due to the relatively larger size of resistor R.sub.6, the equivalent resistance is approximately that of resistor R.sub.E alone.
When control element OPTO2 is on, node 800 is pulled to approximately the voltage level of node 109, preventing transistor Q2 from turning on. Thus, when control element OPTO2 is on, the current limiting circuitry is disabled. If control element OPTO2 is off, transistor Q2 turns on when the voltage across resistor R.sub.E rises to V.sub.BE, the transistor base-emitter turn-on voltage. The maximum current with control element OPT02 off is thus ##EQU4##
While conducting, transistor Q2 provides negative feedback to node 300. The negative feedback substantially prevents the voltage at node 300, and the voltage across resistor R.sub.E, from increasing, thus limiting the current I.sub.DC through resistor R.sub.E. Any increase in voltage is absorbed across resistor R.sub.1, with the relatively negligible excess current passing through transistor Q2.
FIG. 9 illustrates the selectable current limiting DC modes provided by the circuit of FIG. 8. Curve 400 represents the DC mode without the current limiting selected, i.e., with control element OPTO2 turned on. Curve 900 represents the DC mode with current limiting selected, i.e., with control element OPTO2 turned off. Curves 400 and 900 are substantially similar until the current limiting point is reached. Both curves begin at the origin and rise with the slope equal to approximately R.sub.1 +R.sub.2. Darlington transistor pair Q1 turns on when the voltage V is approximately equal to 2V.sub.BE (1+R.sub.1 /R.sub.2), and the current I.sub.DC is equal to approximately 2V.sub.BE /R.sub.2. Once Darlington transistor pair Q1 is turned on, curves 400 and 900 rise with a slope equal to approximately R.sub.E (1+R.sub.1 /R.sub.2). Curve 400 continues at this rate, whereas curve 900 reaches a maximum current as described of approximately V.sub.BE /R.sub.E.
III. Multiple Current--Limiting Modes
As some countries have differing voltage limits for the DC masks, some countries also have different levels of current limiting. Therefore, a maximum current level must be provided for each different current limiting mask. The circuit of FIG. 10 provides for two levels of current limiting by placing a voltage divider with selectable resistance in the current limiting feedback path.
In FIG. 10, the collector of Darlington transistor pair Q1 is coupled to node 121, and the base is coupled to node 300. The emitter of Darlington transistor pair Q1 is coupled via resistor R.sub.E to node 109. Resistor R.sub.1 is coupled between nodes 300 and 121. Capacitor CB and resistor R.sub.2 are coupled in parallel between nodes 300 and 109. The collector of transistor Q2 is coupled to node 300, and the base is coupled to node 800. The emitter of transistor Q2 is coupled to node 109. Resistor R.sub.6 is coupled between the emitter of Darlington transistor pair Q1 and node 800. Resistor R.sub.4 is coupled between node 800 and node 1000. Resistor R.sub.5 and control element OPTO3 are coupled in parallel between node 1000 and node 109.
Transistor Q2 is responsible for limiting the current when the voltage at node 800 reaches the base emitter turn-on voltage V.sub.BE. However, the voltage at node 800 is a function of the voltage at the emitter of Darlington transistor pair Q1 and voltage division between resistor R.sub.6 and resistors R.sub.4 and R.sub.5. When control element OPTO3 is on, voltage division takes place only between resistors R.sub.4 and R.sub.6, whereas when control element OPTO3 is off, voltage division if performed between resistor R.sub.6 and the series resistance of resistors R.sub.4 and R.sub.5. Thus, two selectable values of current limiting are provided.
With control element OPTO3 on, the maximum current is ##EQU5##
With control element OPTO3 off, the maximum current is ##EQU6##
FIG. 11 illustrates the selectable current limiting provided by the circuit of FIG. 10. Curve 1100 represents the DC mode when control element OPTO3 is off. Curve 1101 illustrates the DC mode when control element OPTO3 is turned on. Both curves begin at the origin and rise with a slope of approximately R.sub.1 +R.sub.2 until Darlington transistor pair Q1 turns on at a current I.sub.DC equal to approximately 2V.sub.BE /R.sub.2, and voltage V of approximately 2V.sub.BE (1+R.sub.1 /R.sub.2). After this point, both curves rise at a slope of approximately R.sub.E (1+R.sub.1 /R.sub.2), until the respective maximum current values are reached. Curve 11 reaches a current limit at current I.sub.MAX1 and curve 1101 reaches a current limit at current I.sub.MAX2.
IV. Multiple DC Modes Implemented Using a Plurality of Control Elements
FIG. 12 is a circuit diagram of an artificial inductor which provides for selection between two different voltage levels, selection between current limiting and non-current limiting DC modes, and selection between two current limit values, I.sub.MAX1 and I.sub.MAX2. DC mode selection is accomplished in this embodiment with three control elements: OPTO1, OPTO2, and OPTO3.
In the circuit of FIG. 12, the collector of Darlington transistor pair Q1 is coupled to node 121, and the base is coupled to node 300. The emitter of Darlington transistor pair Q1 is coupled to node 109 via resistor R.sub.E, and node 800 via resistor R.sub.6. Resistor R.sub.1 is coupled between nodes 121 and 300. Resistor R.sub.2 and capacitor CB are coupled in parallel between node 300 and node 109. Resistor R.sub.3 and control element OPTO1 are coupled in series between node 300 and node 109. The collector of transistor Q2 is coupled to node 300, the emitter of transistor Q2 is coupled to node 109, and the base is coupled to node 800. Control element OPTO2 is coupled between node 800 and node 109. Resistor R.sub.4 is coupled between node 800 and node 1000, and resistor R.sub.5 and control element OPTO3 are coupled in parallel between node 1000 and node 109.
Control element OPTO1 is used to select between the two voltage values of the DC characteristics. Control element OPTO2 is used to select between current limiting and non-current limiting DC modes. Control element OPTO3 is used in the current limiting DC modes to select between the two possible maximum current values. The table below identifies the different DC modes of FIG. 12.
__________________________________________________________________________DC MODES OF FIGURE 12OPTO1 OPTO2 OPTO3 V(I.sub.DC) (Q1 = ON) I.sub.MAX__________________________________________________________________________OFF ON -- (I.sub.DC R.sub.E + 2V.sub.BE)(1+ R.sub.1 /R.sub.2) --OFF OFF OFF (I.sub.DC R.sub.E + 2V.sub.BE)(l+ R.sub.1 /R.sub.2) (V.sub.BE /R.sub.E )(1+ R.sub.6 /(R.sub.4 + R.sub.5))OFF OFF ON (I.sub.DC R.sub.E + 2V.sub.BE)(l+ R.sub.1 / (V.sub.BE / R.sub.E )(1+ R.sub.6 /R.sub.4)ON ON -- (I.sub.DC R.sub.E + 2V.sub.BE)(1+ R.sub.1 /(R.sub.2 .vertline. .vertline.R.sub.3) --ON OFF OFF (I.sub.DC R.sub.E + 2V.sub.BE)(1+ R.sub.1 /(R.sub.2 .vertline. .vertline.R.sub.3) (V.sub.BE /R.sub.E )(1+ R.sub.6 /(R.sub.4 + R.sub.5))ON OFF ON (I.sub.DC R.sub.E + 2V.sub.BE)(1+ R.sub.1 /(R.sub.2 .vertline. .vertline.R.sub.3) (V.sub.BE /R.sub.E )(1+ R.sub.6 /R.sub.4)__________________________________________________________________________
FIG. 13 illustrates the different DC modes provided by the circuit of FIG. 12. Curve 400 represents the DC mode when control elements OPTO1 and OPTO2 are off and on, respectively. Curve 1100 represents the DC mode when control elements OPTO1, OPTO2, and OPTO3 are off, off and off, respectively. Curve 1101 represents the DC mode when control elements OPTO1, OPTO2 and OPTO3 are off, off and on, respectively. Curve 600 represents the DC mode when control elements OPTO1 and OPTO2 are on and on, respectively. Curve 1300 represents the DC mode when control elements OPTO1, OPTO2, and OPTO3 are on, off and off, respectively. Curve 1301 represents the DC mode when control elements OPTO1, OPTO2, and OPTO3 are on, off and on, respectively.
Curves 1100 and 1300 provide current limiting at maximum current I.sub.MAX1, whereas curves 1101 and 1301 provide current limiting at maximum current I.sub.MAX2. Curves 400 and 600 are not current limited. Curves 400, 1100 and 1101 begin at the origin and rise with the slope of approximately R.sub.1 +R.sub.2, and transition into a slope of approximately R.sub.E (1+R.sub.1 /R.sub.2) after transistor pair Q1 turns on. For curves 400, 1100 and 1101, transistor pair Q1 turns on at a voltage V of approximately 2V.sub.BE (1+R.sub.1 /R.sub.2), and current I.sub.DC of approximately 2V.sub.BE /R.sub.2.
Curves 600, 1300 and 1301 begin at the origin and rise with a slope approximately R.sub.1 +R.sub.2 .vertline..vertline.R.sub.3, and transition to a slope of approximately R.sub.E (1+R.sub.1 /(R.sub.2 .vertline..vertline.R.sub.3)) after transistor pair Q1 turns on. Transistor pair Q1 turns on for curves 600, 1300, and 1301 at a voltage V of approximately 2V.sub.BE (1+R.sub.1 /(R.sub.2 .vertline..vertline.R.sub.3)), and current I.sub.DC of approximately 2V.sub.BE (R.sub.2 .vertline..vertline.R.sub.3).
FIG. 14 is a circuit diagram of an embodiment of an artificial inductor that provides current limiting and non-current limiting DC modes, as well as two levels of voltage control and two levels of current limiting. An advantage of the circuit of FIG. 14 over that of FIG. 12 is that only two control elements are utilized, thus saving an opto-coupler with its associated cost and space, plus a control line from the modem controller for other purposes.
In FIG. 14, the collector of Darlington transistor pair Q1 is coupled to node 121, and the base is coupled to node 300. The emitter of Darlington transistor pair Q1 is coupled to node 109 via resistor R.sub.E and node 800 via resistor R.sub.6. Resistor R.sub.1 is coupled between nodes 121 and 300. Resistor R.sub.2 is coupled between node 300 and node 1400. Capacitor CB is coupled between node 300 and node 109. The collector, base and emitter of transistor Q2 are coupled to node 300, node 800 and node 1400, respectively. Control element OPTO1 is coupled between node 1400 and node 109, and control element OPTO2 is coupled between 800 and node 109. Npn BJT transistor Q3 is coupled in a diode arrangement with collector and base junctions coupled to node 1400 and the emitter coupled to node 109.
The selectable addition of diode-configured transistor Q3 places a voltage drop of V.sub.BE (approximately 0.7 volts) in series with resistor R.sub.2, and in series with transistor Q2. With the diode enabled, i.e., with control element OPTO1 off, the voltage of the DC characteristic curve undergoes an offset dependent on the diode voltage drop V.sub.BE and the resistor ratio R.sub.1 /R.sub.2. Further, when current limiting is enabled, the maximum current is doubled when transistor Q3 is enabled. The table below identifies the different modes of FIG. 14.
__________________________________________________________________________DC MODES OF FIGURE 14OPTO1 OPTO2 MODE V(I.sub.DC) (Q1 = ON) I.sub.MAX__________________________________________________________________________OFF OFF CURRENT LIMIT (I.sub.DC R.sub.E + V.sub.BE)(1+ R.sub.1 /R.sub.2) + V.sub.BE 2V.sub.BE /R.sub.E LOWOFF ON NORMAL (I.sub.DC R.sub.E + V.sub.BE)(1+ R.sub.1 /R.sub.2) + V.sub.BE -- LOWON OFF CURRENT LIMIT (I.sub.DC R.sub.E + 2V.sub.BE)(1+ R.sub.1 /R.sub.2) V.sub.BE /R.sub.E HIGHON ON NORMAL (I.sub.DC R.sub.E + 2V.sub.BE)(l,+ #/R.sub.2) -- HIGH__________________________________________________________________________
FIG. 15 illustrates the DC modes provided by the artificial inductor circuit of FIG. 14. Curve 400 represents the DC mode when control elements OPTO1 and OPTO2 are on. Curve 900 represents the DC mode when control element OPTO1 is on and control element OPTO2 is off. Curve 1500 represents the DC mode when control element OPTO1 is off and control element OPTO2 is on. Curve 1501 represents the DC mode when control elements OPTO1 and OPTO2 are off.
Curves 400 and 900 begin at the origin and rise at a slope of approximately R.sub.1 +R.sub.2 until Darlington transistor pair Q1 turns on at a voltage V of approximately 2V.sub.BE (1+R.sub.1 /R.sub.2), and current I.sub.DC of approximately 2V.sub.BE /R.sub.2. After transistor pair Q1 turns on, curves 400 and 900 rise at a slope of approximately R.sub.E (1+R.sub.1 /R.sub.2). Curve 900 is current limited at I.sub.MAX1 .apprxeq.V.sub.BE /R.sub.E.
Curves 1500 and 1501 begin at zero current with a voltage V of approximately V.sub.BE due to the diode offset. Curves 1500 and 1501 rise at a slope of approximately R.sub.1 +R.sub.2 until transistor pair Q1 turns on at a voltage V of approximately V.sub.BE (2+R.sub.1 /R.sub.2), and current I.sub.DC of approximately V.sub.BE /R.sub.2. After transistor pair Q1 turns on, curves 1500 and 1501, similarly to curves 400 and 900, rise at a slope of approximately R.sub.E (1+R.sub.1 /R.sub.2). Curve 1501 is current limited at a current I.sub.DC of I.sub.MAX2 .apprxeq.2V.sub.BE /R.sub.E, or approximately two times I.sub.MAX1. It will be obvious that further diodes could be added in series with transistor Q3 to increase the voltage offset of the selectable modes, as well as increasing the value of I.sub.MAX2.
FIG. 16 is another embodiment of an artificial inductor. Advantages over the embodiment of FIG. 14 include temperature compensation for maintaining constant current limiting over a range of operating temperatures, current limit points set by a high-impedance voltage divider circuit to provide independence from the value of resistor R.sub.E, and improved gain for transistor Q2 due to the addition of pnp BJT transistor Q4 and resistor R.sub.7.
In FIG. 16, the collector of Darlington transistor pair Q1 is coupled to node 121, and the base is coupled to node 300. The emitter of Darlington transistor pair Q1 is coupled to node 1601 via resistor R.sub.E1, and to node 109 via resistor R.sub.E. Resistor R.sub.1 is coupled between nodes 121 and 300. Resistor R.sub.2 is coupled between node 300 and node 1400. Capacitor CB is coupled between node 300 and node 109. Transistor Q3 is diode-configured with collector and base junctions coupled to node 1400, and emitter junction coupled to node 109. The collector, base and emitter junctions of transistor Q2 are coupled to nodes 1600, 800 and 1400, respectively.
Resistor R.sub.7 is coupled between node 300 and node 1600. The collector, base and emitter junctions of transistor Q4 are coupled to nodes 109, 1600 and 300, respectively. Resistor R.sub.6 is coupled between nodes 800 and 1601. Resistor R.sub.E2 is coupled between node 1601 and node 1602. Resistor R.sub.E3 and R.sub.TH are coupled in parallel between node 1602 and node 109. Control elements OPTO1 and OPTO2 selectively couple nodes 1400 and 800, respectively, to node 109.
Performance of the circuit of FIG. 16 is similar to that illustrated in FIG. 15. The resistance R.sub.E determines the slope of the DC mode curves for the circuit, due to the smaller size, and therefore greater loading, of resistor R.sub.E relative to resistors RE.sub.1, RE.sub.2, RE.sub.3 and R.sub.TH (R.sub.E is typically 10-100 times smaller). Resistors R.sub.E1, R.sub.E2, R.sub.E3 and R.sub.TH form a voltage divider for the purposes of determining current limiting values. The result is a scaling of the maximum current by a factor of k=1+R.sub.E1 /(R.sub.E2 +R.sub.E3 .vertline..vertline.R.sub.TH). Having the voltage divider function allows for the current limit points to be set independently of the value of R.sub.E. In embodiments without temperature compensation, a single resistor R.sub.E4 may substitute for the combination of resistors R.sub.E2, R.sub.E3 and R.sub.TH (in which case, k=1+R.sub.E1 /R.sub.E4).
Transistor Q4 and resistor R3 provide an extra stage of amplification to transistor Q2. This provides an increase in gain, but does not change the basic functionality thus far described. The table below identifies the different modes of FIG. 16.
__________________________________________________________________________DC MODES OF FIGURE 16OPTO1 OPTO2 MODE V(I.sub.DC) (Q1 = ON) I.sub.MAX__________________________________________________________________________OFF OFF CURRENT LIMIT (I.sub.DC R.sub.E + V.sub.BE)(1 + R.sub.1 /R.sub.2) + V.sub.BE 2kV.sub.BE /R.sub.E LOWOFF ON NORMAL (I.sub.DC R.sub.E + V.sub.BE)(1+ R.sub.1 /R.sub.2) + V.sub.BE -- LOWON OFF CURRENT LIMIT (I.sub.DC R.sub.E + 2V.sub.BE)(1+ R.sub.1 /R.sub.2) kV.sub.BE /R.sub.E HIGHON ON NORMAL (I.sub.DC R.sub.E + 2V.sub.BE)(1+ R.sub.1 /R.sub.2) -- HIGH__________________________________________________________________________ k = 1 + (R.sub.E1 /(R.sub.E2 + R.sub.E3 .vertline..vertline. R.sub.TH))
V. Temperature Compensation
The PN junction of a transistor exhibits a forward voltage drop (V.sub.BE) that is dependent on temperature. Typically, the turn-on base-emitter voltage V.sub.BE has a negative temperature coefficient of approximately minus two millivolts per degree Celsius (-2 mV/.degree. C.) near room temperature. Because the feedback that transistor Q2 provides to limit current I.sub.DC to a prescribed value is of relatively high gain, the current limit point can be sensitive to temperature. To compensate for this sensitivity, a negative temperature coefficient (NTC) resistor (or thermistor), R.sub.TH, is provided in the circuit of FIG. 16.
The temperature dependence of the V.sub.BE turn-on voltage for the typical operating temperature range of twenty-five to seventy degrees is approximately given as:
V.sub.BE (T).apprxeq.0.655-0.00195(T-T.sub.0) �Equation 9!
where T is temperature in degrees Celsius, and T.sub.0 =25.degree.. This linearly modeled relationship is plotted in FIG. 17. The V.sub.BE (T) values shown in FIG. 17 are the base-emitter voltages associated with a constant current flow over temperature for a PN junction of a transistor.
As the device gets hotter, the base-emitter voltage required to generate the same amount of current is reduced, or, equivalently, the amount of current generated at the same voltage increases. To maintain constant feedback current in the circuit of FIG. 16, the voltage V.sub.B,Q2 applied to the base of transistor Q2 must change in a substantially similar temperature-dependent manner as V.sub.BE (T), or:
V.sub.B,Q2 (T).apprxeq.V.sub.BE (T) �Equation 10!
The voltage applied to the base of transistor Q2 is a function of the voltage V.sub.E,Q1 at the emitter of transistor Q1, as determined by a voltage divider circuit. Voltage V.sub.E,Q1 must remain constant for I.sub.MAX to remain constant since V.sub.E,Q1 .apprxeq.I.sub.MAX R.sub.E. Therefore, the voltage divider function provides the temperature compensation. A general equation for the voltage divider function is: ##EQU7## where R.sub.U is the resistance of the upper leg of the voltage divider (R.sub.E1 in the circuit of FIG. 16), and R.sub.L (T) is the resistance of the lower leg of the voltage divider. R.sub.L (T) represents a temperature dependent resistive arrangement. One embodiment of the invention uses thermistors, or negative temperature coefficient (NTC) resistors, to provide the necessary temperature dependence.
Thermistors typically are commercially available in only certain values identified by a reference resistance, r.sub.0, and a constant coefficient, B, which relates to the properties of the material used to construct the thermistor. r.sub.0 is referenced to temperature T.sub.0 =25.degree. Celsius. The logarithmic temperature characteristics of a thermistor are given by: ##EQU8## where temperature T is given in degrees Celsius (with built-in conversion to Kelvin). The logarithmic curve for a thermistor R(T, r.sub.0, B)=R(T, 1000, 3650) is illustrated in FIG. 18.
If the thermistor alone is used to form the lower leg of the voltage divider, the voltage at the base of transistor Q2 is given by: ##EQU9## where R.sub.TH (T) is the thermistor value. A thermistor is chosen having given values for B and r.sub.0, and the resistance R.sub.E1 is selected such that V.sub.BE (25.degree.).apprxeq.V.sub.B,Q2 (25.degree.). Evaluating for typical values: B=4100, r.sub.0 =2000 .OMEGA., V.sub.E,Q1 =1.0V and R.sub.E1 =1060 .OMEGA.; plots of V.sub.B,Q2 (T) and V.sub.BE (T) are provided in FIG. 19. Curve 1900 represents the linearly modeled behavior of V.sub.BE (T), and curve 1901 represents the behavior of the voltage divider with the logarithmic influence of the thermistor.
As shown by FIG. 19, the behavior of curve 1901 does not match that of curve 1900 very well when the voltage divider contains only a thermistor in the lower leg. Further, with freedom primarily only in the selection of resistance R.sub.E1 due to the limited values of thermistors available, the two curves are only guaranteed to match at the design point of 25.degree..
To provide more degrees of freedom, in one embodiment, series resistor R.sub.E2 and parallel resistor R.sub.E3 are coupled to the thermistor, as shown in the circuit of FIG. 16. These added elements allow the voltage curves to match at two or more temperatures. Including elements R.sub.E2 and R.sub.E3 in the lower leg of the voltage divider, the voltage at the base of transistor Q2 is given by: ##EQU10##
To determine the necessary values for R.sub.E2 and R.sub.E3, two temperatures, T.sub.1 and T.sub.2, are selected in the expected range of operation. Given design constraints: V.sub.E,Q1 (from V.sub.E,Q1 =I.sub.MAX R.sub.E), R.sub.E1 (typical value), r.sub.0 and B; the following two simultaneous equations are generated, applying equations �9! and �14!:
V.sub.B,Q2 (T.sub.1).apprxeq.V.sub.BE (T.sub.1)
V.sub.B,Q2 (T.sub.2).apprxeq.V.sub.BE (T.sub.2) �Equations 15-16!
The above simultaneous equations may be solved numerically to determine the two unknowns, R.sub.E2 and R.sub.E3. For example, matching at temperatures 25.degree. and 70.degree. Celsius:
V.sub.BE (25.degree.).apprxeq.0.655V, V.sub.BE (70.degree.).apprxeq.0.567V
Given B=4100 and r.sub.0 =2000 .OMEGA.,
R.sub.TH (25.degree.).apprxeq.2000 .OMEGA., R.sub.TH (70.degree.).apprxeq.329 .OMEGA.
For V.sub.E,Q1 =1.0V, R.sub.E1 =1000 .OMEGA.,
evaluating equations �15-16! for T=25.degree. and 70.degree., and solving for R.sub.E2 and R.sub.E3 yields: R.sub.E2 .apprxeq.1041 .OMEGA. and R.sub.E3 .apprxeq.1501 .OMEGA..
FIG. 20 illustrates the voltage curves for the above example. Curve 1900 represents a plot of V.sub.BE (T), and curve 2000 represents a plot of V.sub.B,Q2 (T). As shown, curves 1900 and 2000 match at the design points P1(25.degree.) and P2(70.degree.). Further, the curves provide satisfactory matching over the range between the design points, and for some temperature values outside of the specified range.
Thus, in conjunction with resistors R.sub.E2 and R.sub.E3, thermistor R.sub.TH serves to compensate the current limit points so that they remain stable over the wide range of temperatures likely to be encountered. This temperature compensation arrangement may be applied to any of the current limiting artificial inductor circuits (e.g., FIGS. 8, 10, etc.) to provide current stability over temperature.
Actual transistor device behavior may differ slightly from the linear modeling of V.sub.BE (T) in equation �9!. Thus, some minor deviation of actual V.sub.BE (T) may occur. Other models may be similarly applied to determine V.sub.BE (T) at the chosen design points. For example, SPICE simulations, using more accurate transistor models, may be used to extract V.sub.BE (T) values.
Further, where V.sub.BE (T) differs when transistor Q3 is enabled in series with transistor Q2, and where more accuracy is desired, the V.sub.BE (T) value with transistor Q3 enabled and the V.sub.BE (T) value without transistor Q3 enabled may be used to determine an intermediate V.sub.BE (T) value at each temperature design point. The respective intermediate V.sub.BE (T) values are then used to derive suitable values for R.sub.E2 and R.sub.E3. For example, using an averaging approach, the intermediate value V.sub.BE (T).sub.INT may be approximated by: ##EQU11## where V.sub.BE, Q3 (T) represents V.sub.BE (T) for transistor Q3 when transistor Q2 is conducting, V.sub.BE,Q2+ (T) represents V.sub.BE (T) for transistor Q2 with transistor Q3 enabled, and V.sub.BE,Q2- (T) represents V.sub.BE (T) for transistor Q2 when transistor Q3 is disabled. Depending on the application, other approaches may also be used as desired to determine an intermediate V.sub.BE (T) value that provides temperature compensation biased towards one current limiting DC mode over another.
Thus, a method and apparatus for implementing DC mode selection have been described. Particular embodiments described herein are illustrative only and should not limit the present invention thereby. The invention is defined by the claims and their full scope of equivalents.

Number	Name	Date
4465981	Pike	Aug 1984
4684880	Chan	Aug 1987
4914402	Dermitzakis et al.	Apr 1990
5047731	Lee	Sep 1991
5051686	Schaffer	Sep 1991

Method and apparatus for implementing DC mode selection in a data access arrangement

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

US Classifications

Field of Search

US

International Classifications

Abstract

Description

Claims

US Referenced Citations (5)