The present invention generally relates to the field of integrated circuit. More specifically, embodiments of the present invention pertain to circuits and methods of improving frequency source's frequency accuracy and frequency stability using Time-Average-Frequency Direct Period Synthesis (TAF-DPS) as the underlying technology.
Clock signal is the most important electrical signal. It directly links to the thing called “time”, which is used to coordinate events inside electronic world. Clock signal is generated from frequency source. Frequency source is found in electronic systems from military, metrology, industrial, consumer, communication networks, automotive, power grid, banking and scientific project. Taking telecommunication industry for example, GPS provided timing supports a variety of applications: a frequency source of 1·10−11 accuracy functions as a primary reference clock for Switched Telephone Networks (STN); time synchronization of microsecond accuracy is used in Cellular Telephone System to synchronize cell sites for allowing seamless switching; Network Time Protocol (NTP) uses millisecond accuracy to support application level usage of accurate time while Precise Timing Protocol (PTP) uses sub-microsecond. IP based applications like streaming audio & video need solid frequency sources for delivering good timing information.
Inside electronic system, clock derives time from frequency. A typical clock system includes a frequency source and a counting circuit (for counting, setting and synchronization). There are two concepts when clocks are used to coordinate events among systems: synchronization and syntonization. Clocks are synchronized when they are agreed in time. Clocks are syntonized when their oscillators have the same frequency. No clock can ever keep perfect time since all oscillators exhibit random and systematic errors. Clock error can be expressed in (1) where T(t) is the time difference between two clocks at time t after synchronization, T0 is synchronization error at t=0, R(t) is the frequency difference between the two clocks' oscillators, ε (t) is the error due to random fluctuations.
T(t)=T0+∫0iR(t)dt+ε(t) (1)
When compared with ideal frequency source, the frequency value of a real source always deviates from the specified value. This imperfection, which is caused by the combined effect of manufacture error, temperature variation, aging, loading shift, is often referred as frequency instability. Commercially there are various types of frequency sources available for choosing, from a few cents XO to a few hundred dollars TCXO (temperature-control crystal) to a few thousand dollars OCXO (oven-controlled crystal). Their performances vary greatly: from XO's tolerance of 10˜100 ppm, to TCXO's˜1 ppm, to OCXO's˜0.1 ppm.
Equation (1) relates frequency error to time error. In many cases, frequency error is caused by frequency instability. In this application the term frequency accuracy is used to represent, in the frequency value of a given frequency source, the difference between actual value and the value specified in its specification. The term frequency stability is used to describe its capability of maintaining its frequency accuracy under the influence of disturbances. The major causes of frequency instability are: temperature step, aging, vibration, shock, oscillator on/off switching and etc. In high performance system, TCXO, or even OCXO, are adopted. Those high quality sources usually have much better frequency stability than low end crystals. The drawback however is the extreme high cost. Out of the causes mentioned above, the frequency instabilities due to temperature and aging can potentially be compensated. Commercial examples for compensating temperature induced instability are available. An example is given in [1] where temperature sensor is used to report temperature reading and built-in fractional-N or integer-N PLL is used to counteract the corresponding frequency deviation. Its resolution of frequency correction is in the range of hundreds Hz. The compensation however is for the particular functional clock (the RF carrier) and the circuit is custom designed. It is hard to be applied to general case.
Time-Average-Frequency Direct Period Synthesis (TAF-DPS) is an emerging frequency synthesis technique [2-3]. Its distinguishing features are small frequency granularity (termed as arbitrary frequency generation) and fast frequency switching (termed as instantaneous frequency switching). Experiment evidence is available to support the claim that its frequency granularity can reach the level of a few ppb [4]. In present application, TAF-DPS is used to develop a scheme for compensating frequency error and improve frequency source's frequency accuracy and frequency stability.
In 2008, a novel concept, Time-Average-Frequency (TAF), is proposed [2]. It removes the constraint that all the cycles in a clock pulse train have to be equal in their length-in-times. As a result, a TAF clock signal can be created by using two, or more, types of cycles. Small frequency granularity can be obtained by adjusting the weighing factor in very fine step. Fast frequency switching is accomplished through directly synthesizing the length of each individual clock pulse. Together, a new technology, Time-Average-Frequency Direct Period Synthesis, is emerged [3]. Its aim is to provide the features of arbitrary frequency generation and instantaneous frequency switching to chip designers and system users.
The important features of arbitrary frequency generation and instantaneous frequency switching enabled by TAF-DPS clock generator are extremely useful for future electronic system designs. They are the enabler for future innovations. In current application those features are used to construct a scheme for improving frequency source's frequency accuracy and frequency stability by compensating frequency error due to temperature deviation, component aging and other disturbances.
This “Discussion of the Background” section is provided for background information only. The statements in this “Discussion of the Background” are not an admission that the subject matter disclosed in this “Discussion of the Background” section constitutes prior art to the present disclosure, and no part of this “Discussion of the Background” section may be used as an admission that any part of this application, including this “Discussion of the Background” section, constitutes prior art to the present disclosure.
It is therefore an object of the present invention to use the TAF-DPS technology for developing a frequency compensation circuit. It is a further object of the present invention to use said TAF-DPS based circuit for improving frequency source's frequency accuracy and frequency stability.
The present invention relates to circuits and methods of using TAF-DPS technology for developing a frequency tuning circuit. Thus, the present invention can take advantage of the excellent frequency generation capability provided by TAF-DPS. As a result, when TAF-DPS frequency compensation scheme is incorporated in electronic systems, a vast majority of such system can benefit from better time synchronization quality in their operations due to higher frequency accuracy and better frequency stability.
Reference will now be made in detail to various embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the following embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be readily apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.
Some portions of the detailed descriptions that follow are presented in terms of processes, procedures, logic blocks, functional blocks, processing, and other symbolic representations of operations on data bits, data streams or waveforms within a computer, processor, controller and/or memory. These descriptions and representations are generally used by those skilled in the arts of VLSI-circuit-and-system design to effectively convey the substance of their work to others skilled in the art. A process, procedure, logic block, function, process, etc., is herein, and is generally, considered to be a self-consistent sequence of steps or instructions leading to a desired and/or expected result. The steps generally include physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical, magnetic, optical, or quantum signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer or data processing system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, waves, waveforms, streams, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise and/or as is apparent from the following discussions, it is appreciated that throughout the present application, discussions utilizing terms such as “processing,” “operating,” “computing,” “calculating,” “determining,” “manipulating,” “transforming,” “displaying”, “compensating”, “correcting”, “calibrating” or the like, refer to the action and processes of a computer or signal processing system, or similar processing device (e.g., an electrical, optical, or quantum computing or processing device), that manipulates and transforms data represented as physical (e.g., electronic) quantities. The terms refer to actions and processes of the processing devices that manipulate or transform physical quantities within the component(s) of a system or architecture (e.g., registers, memories, flip-flops, other such information storage, transmission or display devices, etc.) into other data similarly represented as physical quantities within other components of the same or a different system or architecture.
Furthermore, for the sake of convenience and simplicity, the terms “clock,” “time,” “rate,” “period,” “frequency” and grammatical variations thereof are generally used interchangeably herein, but are generally given their art-recognized meanings. Also, for convenience and simplicity, the terms “data,” “data stream,” “waveform” and “information” may be used interchangeably, as may the terms “connected to,” “coupled with,” “coupled to,” and “in communication with” (each of which may refer to direct or indirect connections, couplings, and communications), as may the terms “electrical path,” “channel,” “wire” (each of which may refer to a physical channel for transferring electrical signal), as may the terms “signal,” “pulse,” “pulse train,” “a sequence of digital data” (each of which may refer to an electrical signal that has only two values: zero and one), as may the terms “input,” “input port,” “input pin” (each of which may refer to a physical channel for receiving data), as may the terms “output,” “output port,” “output pin” (each of which may refer to a physical channel for sending data), as may the terms “frequency resolution,” “frequency granularity,” (each of which may refer to the smallest frequency step), as may the terms “frequency compensation,” “frequency correction,” (each of which may refer to the action of making circuit's output frequency closer to the specified target value), but these terms are also generally given their art-recognized meanings.
Referring now to
The base unit Δ 120 is generated from a plurality of phase-evenly-spaced signals. Referring now to
Refer now to
Referring now to
The TAF-DPS frequency synthesizer output's period can be calculated as TTAF=F·Δ. The control word F can take value in the range of [2, 2K], fraction included. When only integer is used in control word F, the TAF-DPS output is a signal of conventional frequency (i.e. only one type of cycle is used in the clock pulse train). When control word F has fractional part, the TAF-DPS uses Time-Average-Frequency concept in its output signal (i.e. more than one type of cycles can be used in the clock pulse train). The Time-Average-Frequency concept is explained in chapter 3 of reference [3]. The working principle of TAF-DPS can be found in chapter 4 of reference [3]. TAF-DPS frequency synthesizer 400 can function as the circuit block 110 in
The signal CLK_OUT 480 output frequency fs can be calculated using (2) (please see chapter 4 of reference [3]). When divider chain 210 of
Δ=TΔ/K=1/(K·fΔ), fs=1/TTAF=1/(F·Δ)=(K/F)·fΔ (2)
fΔ=fi/K, Δ=1/fi→fs=fi/F (3)
fΔ=N·fi, Δ=1/(K·N·fi)→fs=(K·N/F)·fi (4)
fΔ=fi, Δ=1/(K·fi)→fs=(K/F)·fi (5)
Referring now to
Frequency source's 510 output A is fed into the base time unit 520 to generate a plurality of K phase-evenly-spaced signals D with frequency fΔ 521. The time span between any two logically adjacent signals of said plurality of K phase-evenly-spaced signals is the base time unit Δ. Said signal A can be the signal 211, or 221, or 231 in
Said signal D from base time generator 520 is fed into TAF-DPS synthesizer 530. Synthesizer 530 has an output S whose frequency fs 531 is controlled by frequency control word F 532. From equation (2), frequency fs 531 can be related to frequency fΔ 521 by fs=(K/F)·fΔ. Signal S is inputted into integer-N PLL 540 with a dividing ratio M 542. 540 PLL's output Y has a frequency of fo 541. Frequency fo 541 can be related to frequency fs 531 by fo=M·fs. Equation (6) is therefore derived, which relates the frequency fo of the final output Y to frequency fi of the frequency source's output A. From equation (3), (4) and (5), it is derived that C=1/K for the case of using divider chain to implement base time generator 520, and C=N for the case of PLL, and C=1 for the case of DLL. Therefore, equation (7), (8) and (9) are resulted for the cases of divider chain, PLL and DLL, respectively.
fo=M·fs=(K·M/F)·fΔ=(K·M·C/F)·fi (6)
fo=(M/F)·fi, C=1/K, Divider Chain (7)
fo=(K·N·M/F)·fi, C=N, PLL (8)
fo=(K·M/F)·fi, C=1, DLL (9)
From equation (7), (8) and (9), fo/fi can be expressed as fo/fi=L/F where L is a constant. The control word F has both integer and fraction parts: F=I+r=I·(1+r/I) where r can take either positive or negative value and |r|≤0.5 (this is mathematically equivalent to the description presented in where r is treated as a positive number of 0≤r<1). Therefore, equation (10) can be derived. By properly setting the r and I values, desirable value for fo/fi can be achieved.
fo/fi=L/F=L/[I·(1+r/I)]=(L/I)·[1−r/I+(r/I)2−(r/I)3+ . . . ] (10)
If fo/fi is expressed as fo/fi=(1+x), then x can be regarded as the required amount of frequency compensation (or correction) for making fo=ftarget where ftarget is the target value. In (10), L can be set to any value for user's preference. However, for compensating the frequency error of a frequency source, it is usually set as L=I. Therefore, to the first order, we have equation (11). Equation (11) can be used to help user set the value for I and r. The accuracy of the frequency compensation is to the first order, which is applicable for most real applications since the value of r/I is much smaller than 1% in most practical cases.
x≈−r/I (11)
If, in general, we use ftarget to denote 510 frequency source's target frequency value and fi to denote 510 frequency source's actual output frequency value, equation (12) can represent the relationship between the two values where x is the required amount of correction (i.e. the amount of off-target error). The purpose of the architecture 500 of current invention is to make fo=ftarget. For this reason, to perform the frequency compensation task to first order accuracy, r/I=−x is used to set the parameters I and r. In operation, I is determined first. Thus, r is subsequently set as r=−x·I. When parameters I and r are set using this method, the final output frequency fo 541 and the frequency source's original output frequency fi are related by (13). Equation (13) is good to the first order. Equation (14) is used for accuracy of second order. The value of r can be found from the roots of equation: r2−r·I−x·I2=0. This root of r=(I/2)(1−√{square root over (1+4x)}) will be the solution for meeting the accuracy of second order. For person of ordinary skill in the art, higher order of accuracy can be achieved by using more terms in equation (10).
ftarget=(1x)·fi (12)
x=−r/I, fo/fi=1−r/I, first order (13)
x=−r/I+(r/I)2, fo/fi=1−r/I+(r/I)2, second order (14)
The following example is helpful to understand this frequency compensation scheme. Assume the frequency source is a 100 MHz crystal (target value is ftarget=100 MHz). At one moment, the measured value is fi=99.9997637416 MHz which is about 2.36 ppm (2.362589581·10−6, or ˜236 Hz) off target. A divider chain (please refer to
For some applications, the target frequency ftarget might be higher or lower than the input fi. In other words, the ratio is ftarget/fi=P or ftarget/fi=1/P where P is a value of greater than one. In those cases, fo/fi is expressed as fo/fi=(P+x) for ftarget>fi and fo/fi=(1/P+x) for ftarget<fi. And x can be still regarded as the required amount of frequency compensation (or correction) for making fo=ftarget. In those cases, equation (10) can also be used to calculate the required x value.
An Atlys™ FPGA system is used to verify the architect 500 of present invention. The Atlys circuit board is a complete, ready-to-use digital circuit development system based on a Xilinx Spartan-6 LX45 FPGA, speed grade 3. A 100 MHz crystal from this board serves as the frequency source to be compensated. A divider chain is implemented as a Johnson counter. It functions as the base time generator 420, created from the configurable FPGA elements. There are multiple PLLs available from this FPGA system as standard components. One of them is selected to function as the integer-N PLL 400 in our system. The TAF-DPS is also implemented from the configurable FPGA elements. The circuit for implementing this TAF-DPS is chosen as Flying-Adder frequency synthesis architecture [3]. In this particular case, the implementation approach is HDL coding→simulation→synthesis & map to FPGA. The VHDL code for this Flying-Adder circuit is available in Appendix 4.A of [3].
Referring now to
Referring now to
Referring now to
Plot 851 illustrates an exemplary f vs. temperature curve for a crystal oscillator, for a temperature range from −45° C. to 100° C. Plot 852 depicts the output frequency from the application of present invention 800 of frequency compensation scheme. The same range of f vs. temperature curve is displayed. Comparing plot 851 and 852 it is seen that, after the application of present invention of frequency compensation scheme, the amount of frequency variation is significantly reduce. Plot 861 illustrates the f vs. time curve for a frequency source. In this plot, the frequency deviation due to manufacture error and the frequency drift due to ageing are depicted. Plot 862 shows the same f vs. time curve after the frequency source is compensated by present invention. As shown, the manufacture error related initial frequency deviation is measured first and then compensated using equation (13). In addition, the aging induced frequency error is periodically counteracted by our present invention in a scheduled interval. As a result, the frequency stability is much improved.
The present invention further relates to a method of incorporating the TAF-DPS based frequency compensation scheme inside functional chips. Such chip can be signal processing chip, communication chip, sensor chip, power management chip, general purpose CPU and etc. Refer now to
Chip 900 uses a frequency source 910 as its frequency source. Frequency source 910 has a target frequency value for its operation. In real operating environment, 910 frequency source's output frequency fc usually is not at said target value. TAF-DPS compensation circuit 920 takes 910 source's output as its input and compensates any frequency deviation found in fc. 920 TAF-DPS compensation circuit's output frequency fo is frequency compensated to the target value and it is subsequently used as the reference source for all said PLLs. The architecture of TAF-DPS compensation circuit 920 is described in architecture 500 (please refer to
A TAF-DPS frequency-compensation-scheme-equipped-chip is an electronic system that includes the TAF-DPS frequency compensation scheme. The present invention further relates to a method of using TAF-DPS-frequency-compensation-scheme-equipped-chips as nodes in network for assisting network time synchronization. Refer now to
Chip 1031 also takes output from the frequency reference 1010 as the “good” reference of higher frequency accuracy for comparing its internal time and frequency information with network time and frequency information. The resulting difference is used for 1031 chip's internal TAF-DPS frequency compensation scheme to compensate its frequency error. This task of comparing and compensation is carried out periodically in a prescheduled time interval. This task can also be performed at any time when necessary.
Using 1031 chip's internal timing circuit's output, such as a PLL supported by frequency source 1032 and calibrated by reference 1010, module 1040 generates a clock and time code for supporting 1020 system's operation. Frequency distribution module 1050 takes frequency information from chip 1031 and performs necessary operations and subsequently output frequencies f1 10601, f2 10602, . . . , fn 1060n down the network hierarchy in hierarchical master-salve synchronization architecture. Frequencies f1 10601, f210602, . . . , fn 1060n can also be sent to other nodes of the network in the mutual synchronization architecture. Since the frequency inside chip 1031 has been calibrated against reference 1010, the frequency accuracies of frequencies f1 10601, f210602, . . . , fn 1060n are thus improved and hence their accuracies are better than that of frequency source 1032.
Thus, the present invention provides TAF-DPS based circuits and methods to enhance electronic system's frequency accuracy and frequency stability. Present invention creates a circuit architecture and a scheme for compensating frequency source's frequency error. Present invention discloses a method of incorporating said scheme into processing chip. Present invention further presents a method for using TAF-DPS-frequency-compensation-scheme-equipped chips as nodes in electronic network. As a result, the circuit and apparatus disclosed in present invention can improve electronic system's performance.
The foregoing descriptions of specific embodiments of the present invention have been presented for the purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.
Number | Name | Date | Kind |
---|---|---|---|
6104252 | Hofmann | Aug 2000 | A |
6329850 | Mair | Dec 2001 | B1 |
7065172 | Xiu | Jun 2006 | B2 |
7406144 | Wang | Jul 2008 | B2 |
7764131 | Seth | Jul 2010 | B1 |
7772893 | Chen | Aug 2010 | B2 |
8120389 | Xiu | Feb 2012 | B2 |
8135103 | Courcy | Mar 2012 | B1 |
8664988 | Xiu | Mar 2014 | B1 |
8890591 | Xiu | Nov 2014 | B1 |
9054921 | Mayer | Jun 2015 | B2 |
9118275 | Xiu | Aug 2015 | B1 |
9379714 | Xiu | Jun 2016 | B1 |
9571083 | Rapinoja | Feb 2017 | B2 |
9621173 | Xiu | Apr 2017 | B1 |
20030003887 | Lim | Jan 2003 | A1 |
20050212604 | Cyr | Sep 2005 | A1 |
20060212247 | Shimoyama | Sep 2006 | A1 |
20070104298 | Filipovic | May 2007 | A1 |
20080042766 | Tarng | Feb 2008 | A1 |
20090103604 | Xiu | Apr 2009 | A1 |
20090160493 | You | Jun 2009 | A1 |
20100277246 | Seth | Nov 2010 | A1 |
20110131439 | Renner | Jun 2011 | A1 |
20110207453 | Hsu | Aug 2011 | A1 |
20110285439 | Xiu | Nov 2011 | A1 |
20120209558 | Wilcox | Aug 2012 | A1 |
20120229171 | Xiu | Sep 2012 | A1 |
20140197867 | Xiu | Jul 2014 | A1 |
20150116015 | Toriumi | Apr 2015 | A1 |
20150288368 | Yun | Oct 2015 | A1 |
20160191195 | Magri | Jun 2016 | A1 |
20160360602 | Cheung | Dec 2016 | A1 |
20170072811 | Tabatowski-Bush | Mar 2017 | A1 |
20170194971 | Yonezawa | Jul 2017 | A1 |
20180102180 | Meacham | Apr 2018 | A1 |