Embodiments of the present invention relate to inductor-based circuits. More specifically, embodiments of the present invention relate to a method and apparatus for improving inductor performance using multiple strands with transposition.
Spiral inductors are important components of many high-frequency circuits such as voltage controlled oscillators, low noise amplifiers, mixers, and other components. Generally, a high quality factor, Q, is desirable for high performance. A high quality factor translates to lower phase noise in voltage controlled oscillators and a lower noise figure in low noise amplifiers.
The quality factor is a function of energy stored, which may be defined by the difference between peak magnetic energy and peak electric energy, and the energy loss in one oscillation cycle. The quality factor is limited by energy stored in parasitic capacitance, ohmic loss in the inductor windings, and energy loss in the substrate. Resistance in the inductor windings increases with frequency due to skin effect and proximity effect which causes significant degradation in the inductor's quality factor.
The skin effect causes AC current to crowd towards a surface of an inductor winding due to self induction. The proximity effect causes AC current to crowd towards the outer edges of parallel lines due to mutual induction. The skin effect and proximity effect are caused by eddy currents which are induced by time-varying magnetic field. Eddy currents flow in a direction that produces an opposing magnetic field. Eddy currents combine with applied currents and result in current crowding on edges of lines.
Prior approaches of increasing the width of an inductor winding had limited benefits since most AC current flows along the sides of the winding due to the lateral skin effect and proximity effect. Also, the utilization of multiple metal levels for winding had limited benefit because most AC current flows through the top surface of the top metal and the bottom surface of the bottom metal in an inductor metal stack.
According to an embodiment of the present invention, an inductor winding is split into multiple strands. The strands may be split laterally and/or vertically. According to one aspect of the present invention, the strands are transposed along the length of the winding. According to another aspect of the present invention, the strands are transposed such that all possible positions in the winding cross section are occupied equally or approximately the same distance along the length of the winding.
The features and advantages of the present invention are illustrated by way of example and are by no means intended to limit the scope of the present invention to the particular embodiments shown.
a-d illustrates a spiral inductor with vertical transposition according to an exemplary embodiment of the present invention.
a-4c illustrate cross-sectional views at positions of the multi-stranded magnetic component of
a-6c illustrate cross-sectional views at positions of the multi-stranded magnetic component of
In the following description, for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that specific details in the description may not be required to practice the embodiments of the present invention. In other instances, well-known circuits, devices, and programs are shown in block diagram form to avoid obscuring embodiments of the present invention unnecessarily. Additionally, some embodiments of the invention are described in the context of field programmable gate arrays (“FPGA”), but the invention is applicable to other contexts as well, including other semiconductor devices such as programmable logic devices, complex programmable logic devices, application specific integrated circuits, processors, controllers and memory devices.
The target device 100 includes a plurality of logic-array blocks (LABs). Each LAB may be formed from a plurality of logic blocks, carry chains, LAB control signals, (lookup table) LUT chain, and register chain connection lines. A logic block is a small unit of logic providing efficient implementation of user logic functions. A logic block includes one or more combinational cells, where each combinational cell has a single output, and registers. According to one embodiment of the present invention, the logic block may operate similarly to a logic element (LE), such as those found in Stratix® devices manufactured by Altera Corporation, or a combinational logic block (CLB) such as those found in Virtex devices manufactured by Xilinx Inc. In this embodiment, the logic block may include a four input lookup table (LUT) with a configurable register. According to an alternate embodiment of the present invention, the logic block may operate similarly to an adaptive logic module (ALM), such as those found in Stratix devices manufactured by Altera Corporation. LABs are grouped into rows and columns across the target device 100. Columns of LABs are shown as 111-116. It should be appreciated that the logic block may include additional or alternate components.
The target device 100 includes memory blocks. The memory blocks may be, for example, dual port random access memory (RAM) blocks that provide dedicated true dual-port, simple dual-port, or single port memory up to various bits wide at up to various frequencies. The memory blocks may be grouped into columns across the target device in between selected LABs or located individually or in pairs within the target device 100. Columns of memory blocks are shown as 121-124.
The target device 100 includes digital signal processing (DSP) blocks. The DSP blocks may be used to implement multipliers of various configurations with add or subtract features. The DSP blocks include shift registers, multipliers, adders, and accumulators. The DSP blocks may be grouped into columns across the target device 100 and are shown as 131.
The target device 100 includes a plurality of input/output elements (IOEs) 140. Each IOE feeds an I/O pin (not shown) on the target device 100. The IOEs are located at the end of LAB rows and columns around the periphery of the target device 100. According to an embodiment of the present invention, the IOEs 140 are high speed serial IOEs. Each IOE includes a bidirectional I/O buffer and a plurality of registers for registering input, output, and output-enable signals. When used with dedicated clocks, the registers provide performance and interface support with external memory devices. According to an embodiment of the present invention, each of the IOEs 140 may also include a voltage controlled oscillator having a spiral inductor. The spiral inductor may be a multi-stranded spiral inductor utilizing vertical and/or lateral transposition.
The target device 100 may include routing resources such as LAB local interconnect lines, row interconnect lines (“H-type wires”), and column interconnect lines (“V-type wires”) (not shown) to route signals between components on the target device.
a-d illustrate a layout view of a four layer spiral inductor with vertical transposition according to an exemplary embodiment of the present invention. Layer 201 shown in
a illustrates a first strand coupled to terminal 218 and 219 on track 205. The first strand includes strand segment 210 which resides on track 205, strand segment 211 which resides on track 206, strand segment 212 which resides on track 207, strand segment 213 which resides on track 208, strand segment 214 which resides on track 207, strand segment 215 which resides on track 206, and strand segment 216 which resides on track 205. As illustrated, crossing segment 251 transposes the first strand from track 205 on layer 201 to track 206 on layer 202. Crossing segment 252 transposes the first strand from track 206 on layer 202 to track 207 on layer 203. Crossing segment 253 transposes the first strand from track 207 on layer 203 to track 208 on layer 204. Crossing segment 254 transposes the first strand from track 208 on layer 204 to track 207 on layer 203. Crossing segment 255 transposes the first strand from track 207 on layer 203 to track 206 on layer 202. Crossing segment 256 transposes the first strand from track 206 on layer 202 to track 205 on layer 201.
A second strand is coupled to terminals 228 and 229 which resides on track 206. The second strand includes strand segment 220 which resides on track 206, strand segment 221 which resides on track 205, strand segment 222 which resides on track 206, strand segment 223 which resides on track 207, strand segment 224 which resides on track 208, and strand segment 225 which resides on track 207. As illustrated, crossing segment 261 transposes the second strand from track 206 on layer 202 to track 205 on layer 201. Crossing segment 262 transposes the second strand from track 205 on layer 201 to track 206 on layer 202. Crossing segment 263 transposes the second strand from track 206 on layer 202 to track 207 on layer 203. Crossing segment 264 transposes the second strand from track 207 on layer 203 to track 208 on layer 204. Crossing segment 265 transposes the second strand from track 208 on layer 204 to track 207 on layer 203.
A third strand is coupled to terminals 238 and 239 on track 207. The third strand includes strand segment 230 which resides on track 207, strand segment 231 which resides on track 208, strand segment 232 which resides on track 207, strand segment 233 which resides on track 206, strand segment 234 which resides on track 205, and strand segment 235 which resides on track 206. As illustrated, crossing segment 271 transposes the third strand from track 207 on layer 203 to track 208 on layer 204. Crossing segment 272 transposes the third strand from track 208 on layer 204 to track 207 on layer 203. Crossing segment 273 transposes the third strand from track 207 on layer 203 to track 206 on layer 202. Crossing segment 274 transposes the third strand from track 206 on layer 202 to track 205 on layer 201. Crossing segment 275 transposes the third strand from track 205 on layer 201 to track 206 on layer 202.
A fourth strand is coupled to terminals 248 and 249 on track 208. The fourth strand includes strand segment 240 which resides on track 208, strand segment 241 which resides on track 207, strand segment 242 which resides on track 206, strand segment 243 which resides on track 205, strand segment 244 which resides on track 206, strand segment 245 which resides on track 207, and strand segment 246 which resides on track 208. As illustrated, crossing segment 281 transposes the fourth strand from track 208 on layer 204 to track 207 on layer 203. Crossing segment 282 transposes the fourth strand from track 207 on layer 203 to track 206 on layer 202. Crossing segment 283 transposes the fourth strand from track 206 on layer 202 to track 205 on layer 201. Crossing segment 284 transposes the fourth strand from track 205 on layer 201 to track 206 on layer 202. Crossing segment 285 transposes the fourth strand from track 206 on layer 202 to track 207 on layer 203. Crossing segment 286 transposes the fourth strand from track 207 on layer 203 to track 208 on layer 204.
Strands A, B, C, and D compose the winding of the magnetic component 300 and are vertically transposed through each of the tracks on magnetic component. Crossing segment 311 transposes strand A from track 301 to track 302. Crossing segment 312 transposes strand A from track 302 to track 303. Crossing segment 313 transposes strand A from track 303 to track 304. Crossing segment 314 transposes strand A from track 304 to track 303. Crossing segment 315 transposes strand A from track 303 to track 302. Crossing segment 316 transposes strand A from track 302 to track 301.
Crossing segment 321 transposes strand B from track 301 to track 302. Crossing segment 322 transposes strand B from track 302 to track 303. Crossing segment 323 transposes strand B from track 303 to track 304. Crossing segment 324 transposes strand B from track 304 to track 303. Crossing segment 325 transposes strand B from track 303 to track 302.
Crossing segment 331 transposes strand C from track 303 to track 304. Crossing segment 332 transposes strand C from track 304 to track 303. Crossing segment 333 transposes strand C from track 303 to track 302. Crossing segment 334 transposes strand C from track 302 to track 301. Crossing segment 335 transposes strand C from track 301 to track 302. Crossing segment 336 transposes strand C from track 302 to track 303.
Crossing segment 341 transposes strand D from track 304 to track 303. Crossing segment 342 transposes strand C from track 303 to track 302. Crossing segment 343 transposes strand D from track 302 to track 301. Crossing segment 344 transposes strand D from track 301 to track 302. Crossing segment 345 transposes strand D from track 302 to track 303. Crossing segment 346 transposes strand D from track 303 to track 304. In this example, 4 strands are supported by tracks 301-304. These strands are unique and electrically isolated from one another. According to an embodiment of the present invention, the electrical isolation provides that there is no DC current path between any two strands except at the terminals.
a-4c illustrates cross-sectional views at positions of the multi-stranded magnetic component of
b illustrates a cross-sectional view of the multi-stranded magnetic component 300 (shown in
c illustrates a cross-sectional view of the multi-stranded magnetic component 300 (shown in
The magnetic component 500 includes a plurality of strands which compose the winding of the magnetic component. Each of the strands span the length of the winding and are both are vertically and laterally transposed through each of the tracks on the magnetic component. Crossing segment 511 transposes strand 510 from track 501 to track 505. Crossing segment 512 transposes strand 510 from track 505 to track 506.
Crossing segment 521 transposes strand 520 from track 502 to track 501. Crossing segment 522 transposes strand 520 from track 501 to track 505. Crossing segment 523 transposes strand 520 from track 505 to track 506. Crossing segment 531 transposes strand 530 from track 503 to track 502. Crossing segment 532 transposes strand 530 from track 502 to track 501. Crossing segment 533 transposes strand 530 from track 501 to 505. Crossing segment 541 transposes strand 540 from track 504 to track 503. Crossing segment 542 transposes strand 540 from track 503 to track 502. Crossing segment 543 transposes strand 540 from track 502 to track 501.
Other crossing segments and strands are also illustrated in
a-6c illustrate cross-sectional views at positions of the multi-stranded magnetic component of
b illustrates a cross-sectional view of the multi-stranded magnetic component 500 (shown in
c illustrates a cross-sectional view of the multi-stranded magnetic component 500 (shown in
The crossing segments illustrated in
The multi-stranded magnetic component illustrated in
The magnetic component 700 includes a plurality of strands which compose the winding of the magnetic component. Each of the strands span the length of the winding and are both are vertically and laterally transposed through each of the tracks on the magnetic component. The black squares on the strand segments represent vias or via arrays to metal levels below.
According to embodiments of the present invention, magnetic component winding is split into multiple strands to create a planar litz wire. The strands are kept electrically isolated except at the end of windings. The strands are transposed (twisted, woven, braided) along a length of the winding. In one embodiment, all possible positions (tracks) in the winding cross section are occupied equally. Transposition may occur laterally and/or vertically for multi-level metal implementations. The technique disclosed for magnetic component winding may used for inductors, transformers, balun, or other magnetic components which experiences skin and proximity effects. The transposition scheme may be applied to single turn or multi-turn magnetic components. Embodiments of the present invention may improve the high-frequency Q of spiral inductors by reducing skin effect and proximity effect. Higher Q spiral inductors enable lower phase noise of voltage controlled oscillators and improved performance of other inductor-based circuits.
In the foregoing specification embodiments of the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the embodiments of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.
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