Claims
- 1. A noise-suppression circuit for improving immunity to noise due to cross-coupling between independent first and second single-ended output control lines of a dynamic logic circuit having independent mutually exclusive first and second control signals thereon, said noise-suppression circuit comprising:a first FET having a drain coupled to said first single-ended output control line of said dynamic logic circuit and a gate coupled to said second single-ended output control line of said dynamic logic circuit; and a second FET having a drain coupled to said second single-ended output control line and a gate coupled to said first single-ended output control line; and wherein said first FET actively suppresses high-going pulses on said first single-ended output control line when said first single-ended output control line is low, and said second FET actively suppresses high-going pulses on said second single-ended output control line when said second single-ended output control line is low.
- 2. The noise suppression circuit of claim 1, wherein:said first FET comprises an NMOSFET having a source coupled to a circuit ground; and said second FET comprises an NMOSFET having a source coupled to the circuit ground.
- 3. A method for improving noise immunity from cross-coupling between independent first and second single output control lines of a dynamic logic circuit having independent mutually exclusive first and second control signals thereon, comprising:coupling a drain of a first FET to said first single-ended output control line and a gate of said first FET to said second single-ended output control line, wherein said first FET actively suppresses noise on said first single-ended output control line; and coupling a drain of a second FET to said second single-ended output control line and a gate of said second FET to said first single-ended output control line, wherein said second FET actively suppresses noise on said second single-ended output control line.
CROSS REFERENCE TO RELATED APPLICATION
This is a divisional of application Ser. No. 08/658,920 filed on May 31, 1996 now U.S. Pat. No. 5,886,540.
The present patent application is a divisional of U.S. application having Ser. No. 08/658,920, entitled EVALUATION PHASE EXPANSION FOR DYNAMIC LOGIC CIRCUITS, which is incorporated herein by reference.
US Referenced Citations (9)
Foreign Referenced Citations (1)
Number |
Date |
Country |
61-224623 |
Oct 1986 |
JP |