Method and apparatus for improving the performance of delta-sigma modulators

Abstract

A delta-sigma modulator that provides improved SNR performance in applications such as low-power mobile wireless communications and high frequency radar applications is disclosed. Multiple comparators 10, each comprising a sequence of three latches 20, 22, 24, connect the modulator's input filter circuit 12 to the modulator's output interfaces 14, providing quantization of the integrated, filtered signal provided by the filter circuit 12. A clock signal having a cycle period Tc enables a first latch 20 connected to the signal input of each comparator 10 to provide a digital signal to the signal input of a second latch 22. The second latch 22 supplies a digital signal to a third latch 24 in the sequence, in response to the signal received from the first latch 20, by a lagged clock signal derived from the given clock signal Tc by providing a first lag time TL where Tc/2≧TL>0. A third latch in the sequence is enabled by a clock signal having a second lag time TS=Tc/2+TE, and the delay TE<

Description

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention is related to analog to digital converter devices. More particularly, the present invention pertains to comparator devices used for digital signal generation.

[0004] 2. Discussion of Related Art

[0005] The increasing importance of high-capacity wireless data communications has generated a demand for accurate, fast, and low-power-dissipation analog-to-digital converters to change high frequency analog inputs to digital signal formats. Delta-sigma modulators (DSMs) are often used to digitize signals having large dynamic range requirements, and have a wide variety of wireless applications, ranging from radar devices to low-power mobile communications. However, even though recent advances in very-large-scale circuit integration (VLSI) have provided low-cost, low-power implementations of the digital signal postprocessing associated with these DSMs, the comparator delay times and power parameters required for providing an adequate signal-to-noise ratio (SNR) for the DSMs has limited their usefulness.

[0006] A conventional delta-sigma modulator, shown in FIG. 1, uses one or more parallel comparator circuits 10 connecting a noise-shaping filter circuit 12, which provides the analog sum of an input signal stream Sin and respective analog feedback signals Fa, to the interface circuits 14 that produce one or more one-bit, two-level digital feedback signals Fb. The feedback signals F1, . . . Fn, provided as digital signals Fb by the interface circuits 14 in response to respective bit stream voltage signals Vb1, . . . Vbn output by the respective comparators 10, are converted to analog feedback signals Fn by respective digital to analog converters (DACs) 16 and fed back on respective paths to respective input points in the filter circuit 12, as is well-known in the art. The output of the DSM provides multiple digital output signal streams S1, . . . Sn in response to a sample clock signal having a given period Tc, and respective bit stream voltage signals Vb1, . . . Vbn. Each DSM comparator 10 shown in FIG. 1 has a respective distinctive trip-point threshold Th1, . . . Thn set by a respective input resistance value R1 . . . Rn.

[0007] Conventional comparator circuits 10 used in DSMs consist of a sequence of two or three transparent latch stages enabled by alternate phases of the sample clock signal Tc, as shown in FIGS. 1a and 1b. In FIG. 1, each comparator produces an output voltage Vb in each of the sampling intervals ti determined by the sample clock signal Tc, in response to the analog signal V(t) input by the filter circuit 12 to the comparator and the threshold Th of the individual comparator 10 determined by the respective resistance value R1, . . . Rn, so that each sample is quantized as one bit Vb(ti) in a digital bit stream bk for each of the intervals kti, as shown in FIG. 1c. Each bit Vb(ti) in the bit stream bk output by an ideal comparator is defined as: 1$\begin{array}{cc}{b}_k=\{\begin{array}{c}+1\mathrm{if}V\left(t\right)\le 0\\ -1\mathrm{if}V\left(t\right)>0\end{array}& \left(1\right)\end{array}$

[0008] However the performance limitations of conventional comparator circuits result in deviations from this ideal behavior. In particular, quantization latency Tq and the probability of a metastable state causing a comparator error Pmeta interact to limit the signal-to-noise SNR performance that can be achieved in DSM circuit designs having given frequency response and power efficiency parameters. The quantization latency Tq is the time that elapses between the occurrence of a sampled value at a time ti, and the occurrence of the smallest unambiguous comparator output voltage VL at the comparator output, which is shown schematically in FIG. 1c.

[0009] It can be considered a given that output error probability is P=2VL/AQ, as explained by C. E. Woodward, et al. in IEEE Journal of Solid State Circuits, vol. SC-10 (December 1975) at p. 392. There, VL is the smallest unambiguous level for the comparator outputs Vb1 thru Vbn, Q is the least significant bit (LSB) voltage, e.g., the minimum value of the difference between the thresholds (Thi+1−Thi) corresponding to the resistances Ri, . . . Rn shown in FIG. 1, and A is the gain of a comparator 10. Then, where t is the time after a latch command provided by the clock signal Tc input to that comparator and τ is the regeneration time constant of the first latch stage 20 in that comparator: 2$A=\{\begin{array}{c}{A}_o,t<0\\ A_o{e}^{t/\tau },t\ge 0\end{array}$

[0010] Thus it can be demonstrated that, for input signal values V(t) that are uniformly distributed, the probability Pmeta is exponentially related to latency Tq:

P meta =P o exp(−Tq/τ)  (2)

[0011] It is important to note that the value of the regeneration time constant τ in equation #2 is independent of Pmeta and Tq, and varies with the parasitic capacitances associated with the transistors in the first stage in a manner well-known in the art. Therefore Pmeta is an inverse function of Tq, when both are expressed as a multiples of τ, as is discussed in greater detail with reference to FIG. 5 below. Thus, in general, Pmeta increases as Tq decreases, and decreases as Tq increases, as shown in FIG. 3a, thereby providing a trade-off that sacrifices either frequency response or SNR, as indicated by FIG. 3b.

[0012] This quantization latency Tq in a comparator's bit stream (bk) can be reduced, for low-frequency signals, without increasing Pmeta by adjusting the coupling of the respective feedback signal Fa into the filter circuit 12 from the interface circuits 14 in a manner well-known in the art. However, given that fc=1/Tc, at higher signal frequencies where Tq>Tc/2 that conventional compensation method is ineffective. The maximum usable signal frequency fmax provided by the conventional method is approximately: 3$\begin{array}{cc}{f}_{\max }\approx \frac{1}{4T_q}& \left(3\right)\end{array}$

[0013] Metastability errors are produced by the comparator's inability to promptly make a conclusive bit decision when the comparator's input sample V(t) is in a gray area Vg defined as Vg=2VL/Ao, where VL is the smallest unambiguous comparator output and Ao is the DC gain of the comparator. In this gray area Vg there is some small but significant probability that the output of the comparator will remain at an indeterminate level between the 0 and 1 digital states after the expected transition time Tr, as shown in FIG. 2b. Thus the metastability Pmeta of each comparator's digital output Vb is a function of what voltage V(t) is provided by the filtered analog signal input to that comparator input in each sampling interval ti.

[0014] Metastability is a critically important factor in the design of synchronizer circuits, where it compromises the reliability of the output signals' synchronization. In synchronizer circuit design, metastability has been measured as the number of indeterminate states occurring when a predetermined lag time is provided between the nominal clock pulse of the output of a synchronizer flipflop connected to the input of a second flipflop driven by a sample clock signal Tc. See J. U. Horstmann, et al., “Metastability Behavior of CMOS ASIC Flip-Flops in Theory and Test”, IEEE Journal of Solid State Circuits, vol. 24, no. 1 (February 1989), pp. 146-157. Ideally, of course, no errors would occur in the output that these synchronizers produce after the expected transition time Tr. Thus, in practice, metastability errors in these synchronizers can be reduced at the expense of an increase in quantization latency Tq from a point between ti and Tr to a later point, even beyond Tr in FIG. 2b. However, this reduces the suitability of these synchronizers for use in high-frequency applications, applications that implementing frequencies above the conventional fmax values provided by these circuits. This theoretical trade-off between latency and metastability is illustrated graphically in FIG. 3a.

[0015] After all possible error corrections have been made, the SNR achievable by a DSM is a function of the probability of metastability error events Pmeta, as shown in FIG. 3b. Because all metastability errors are probabilistic rather than deterministic events, these errors cannot be effectively corrected or compensated, they must be prevented. See, J. A. Cherry et al., “Clock Jitter and Quantizer Metastability in Continuous-Time Delta-Sigma Modulators,” IEEE Transactions on Circuits and Systems, vol. 46 no. 6 (June 1999), pp. 661-676. However, to use DSMs in many popular applications, the DSMs' conventional Tq values must be reduced, not increased, so that fmax can be increased.

[0016] In FIG. 3b, the position of this SNR/Pmeta trade-off curve is independent of the interval Tc provided by the comparators' sample clock frequency fc. Instead, it is a function of the design parameters of the DSM circuit, particularly the permissible rate of power consumption, and the integrated circuit technology used to implement the modulator. Specifically, Tq and Pmeta in conventional comparator circuit designs are both a function of the number of latch stages (n) used in the comparator circuit, and can be expressed as:

T q =a+T c (n−2)/2  (4)

[0017] and

P meta =b exp(−c[a+Tc(n−2)/2])  (5)

[0018] where the coefficients “a, b, c” are design-specific constants such that, where n is the number of latches and n≧2 they are: a=Tq for n=2, b=Po, c=1/τ. These constants are independent of the parameters affected by the present invention, and “exp” indicates that the subsequent parenthetical expression is an exponential function.

[0019] However, only a small subset of the points along the tradeoff curve shown in FIG. 3a are implemented by practice of adding latch stages to conventional comparator circuits, points that correspond to the cumulative delays produced by half-integer multiples of Tc, as shown in FIG. 4. The first two points correspond to the performance provided by two and three-stage implementations found in the prior art. The subsequent points in FIG. 4 correspond to additional latch stages proposed by J. A. Cherry, et al., (supra).

[0020] Continuous-time delta-sigma modulators (CT-DSMs), in particular, are advantageous for radar and popular low-power, high frequency digital mobile telecommunications applications because they can potentially provide higher resolution at a lower power consumption rate than discrete-time modulators. Unfortunately, the continuous-time DACs used in CT-DSMs increase the CT-DSMs' sensitivity to the metastability errors occurring during quantization. However, the additional stages proposed by J. A. Cherry, et al. to reduce metastability in continuous-time modulators significantly increase the modulators' power consumption. Thus, at least in theory, both the operating frequency and the power efficiency advantages of CT-DSMs are limited by the need to reduce the occurrence of metastability errors in CT-DSMs.

[0021] In low-pass DSM devices where fmin=0, the comparator latency Tq required to achieve an acceptable metastability error rate is a small fraction of the period of the highest signal frequency input to the modulator, reducing the probability Pmeta of sample values in grey area Vg. However, in band-pass modulators, where fmax≈fmin, the latency Tq may occupy a large portion of the period Tc available at center frequency (fctr) of the bandpass signal. As the latency approaches one-half of the period of output signal's frequency Tc/2, it becomes difficult to achieve stability in the feedback loop in these DSM devices.

[0022] The conventional trade-offs that increase quantization latency and the number of latch stages to reduce the incidence of these non-correctable probabilistic metastability errors in CT-DSMs reduce their operating frequency, and elevate the power consumption rate, respectively. Since many popular CT-DSM applications, such as the low-power, high-frequency GSM and PCS digital mobile telecommunications devices, require both increased high frequency capability and minimal power consumption, some other means of reducing metastability errors is needed.

SUMMARY OF THE INVENTION

[0023] In accordance with the present invention the performance of a DSM is improved by an invention reducing the metastability errors produced by a comparator, wherein a second latch in the comparator is enabled with a delayed clock signal that has a lag TL relative to a clock signal that enables a first latch in the comparator to produce a first latch signal, such that TL≠nTc/2 and TL≠0. The second latch is connected to the first latch and adapted to be enabled by the delayed clock signal to produce a second latch signal in response to a latch input signal produced in response to said first latch signal.

[0024] In one particular embodiment TL=TE, Tc/2>TE>0, where a third latch subsequent to the second latch is enabled by the logical complement of the delayed clock signal having a lag time Ts relative to the clock signal that enables the first latch such that Tc>Ts>Tc/2.

[0025] Preferably the delayed clock signal is provided by adding a delay time TE to the clock signal that enables the first latch.

[0026] In another particular embodiment TL=TE+Tc/2, where Tc/2>TE>0 and a third latch subsequent to the first latch is enabled by the logical complement of the clock signal having a lag time of Tc/2 relative to the clock signal that enables the first latch.

[0027] Preferably the delayed clock signal is provided by adding a delay time TE to the logical complement of the clock signal that enables the first latch.

[0028] In one particular embodiment the clock signal having a lag time of Tc/2 relative to the clock signal that enables the first latch is provided by inverting that clock signal.

[0029] In a modulator circuit in accordance with the present invention a comparator connects the output of the filter circuit to the input of the modulator's output interface circuit. The comparator includes a first latch connecting the output of the filter circuit to a second latch. The first latch is enabled to produce a first latch signal in response to a signal on the output of the filter circuit by a given clock signal having a given phase and a given cycle period Tc. The second latch is enabled by a delayed clock signal having a lag time TE such that Tc/2>TE>0 to produce a second latch signal in response to said first latch signal.

[0030] Quantization in accordance with the present invention supplies an analog signal to a first latch that is enabled by a clock signal having a clock period Tc to produce a first latch signal in response to said analog signal. A second latch is enabled by a delayed clock signal offset by a lag time TE relative to the start of each clock period such that Tc/2>TE>0 to produce a second latch signal in response to said first latch signal. In a particular embodiment, a third latch is enabled by a phase of said delayed clock signal opposite to a given phase that enables the second latch, to produce a third latch signal in response to said second latch signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The features and advantages of the present invention will be better understood and appreciated when the detailed description provided below is considered in conjunction with the figures provided, wherein:

[0032] FIG. 1 is a single-line schematic diagram of a delta-sigma modulator in accordance with the prior art;

[0033] FIGS. 1 a and 1b are schematic diagrams of conventional prior art two and three-stage comparators, respectively, for use in the modulator shown in FIG. 1;

[0034] FIG. 1 c is a schematic signal diagram for a conventional prior art comparator showing the quantization latency Tq;

[0035] FIG. 2 a is a schematic signal diagram showing the ideal response of the output of a comparator to the input signal shown in FIG. 1c;

[0036] FIG. 2 b is a schematic signal diagram showing a metastability error in the response of the output of a comparator to the input signal shown in FIG. 1c;

[0037] FIG. 3 a illustrates the relationship between a comparator's probability of metastability errors and a conventional prior art comparator's quantization latency;

[0038] FIG. 3 b illustrates the relationship between the probability of metastability errors and the signal-to-noise ratio of the signal output by a conventional prior art comparator;

[0039] FIG. 4 illustrates the metastability tradeoffs available in accordance with the prior art;

[0040] FIG. 5 a is a two-line schematic circuit diagram of a D-type differential latch circuit used in DSM comparators;

[0041] FIGS. 5 b and 5c are one-line block diagrams of respective embodiments of a comparator in accordance with the present invention for use in the DSM modulator shown in FIG. 1;

[0042] FIGS. 5 d and 5e are timing diagrams for comparators in accordance with the embodiments of the present invention shown in FIGS. 5b and 5c, respectively;

[0043] FIG. 5 f is a flow diagram model of a three-latch continuous-time, continuous-valued comparator;

[0044] FIG. 6 is a distribution diagram showing the transient response performance of a prior art comparator in SPICE delta-sigma modulator simulation trials; and

[0045] FIG. 7 is a distribution diagram showing the transient response performance of a comparator in accordance with the present invention in that SPICE delta-sigma modulator simulation.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] Each of the comparators 10 used in delta-sigma modulators (DSMs) is made up of at least three latch stages as shown in FIGS. 5b and 5c. Each latch stage is preferably a D-type transparent latch the same or similar to the bipolar latch circuit shown in FIG. 5a. The input to the first latch stage 20 in each comparator 10 is effectively analog, in contrast to the digital outputs provided to each subsequent latch stage in the comparator 10. Also, the first stage 20 of each comparator 10 in the DSM has a respective distinctive trip point, so that each comparator produces a respective distinctive stream of bits (bk) as its output (Vb).

[0047] The first latch stage 20 in each comparator circuit 10 samples the input signal at the falling edge of the clock signal and regenerates the input signal to a valid logic level. The last stage 24 in each comparator 10 provides a current source that permits the comparator's output S1-Sn to slew between the given voltage levels that define logic levels 1 and 0 at a high rate, while driving the interface circuit 14, which includes six D/A converter cells and an output encoder cell in a presently preferred embodiment.

[0048] As shown in the two-line schematic in FIG. 5a, each latch stage 20, 22, 24 in each comparator circuit 10 in the DSM is controlled by a differential transistor pair Q1 and Q2. Q1 and Q2 steer a tail current provided through R1 to one of two amplifier circuit paths in the latch 20, depending on the phase of the clock signal Tc, shown as a single line in FIGS. 5b and 5c and here represented by the clock signal provided to the Tc+ input and the complementary signal provided to the Tc− input. In the high phase of the clock signal Tc, the latch stage 20, 22, 24 is in a transparent state. In the transparent state (T) the differential transistor pair Q3 and Q4 in the first path of the latch 20 supply amplified signals representing the input signals applied to complementary inputs In+ and In− to the complementary outputs Out+ and Out−. In the low phase of the clock signal Tc, the tail current is steered into a cross-coupled differential pair Q5 and Q6 in the second path. Positive feedback provided by this cross-coupled pair regenerates the signal already present at the latch outputs Out+ and Out−. That is, in the regeneration state (R), the differential voltage between the collectors of Q5 and Q6 continuously increases during this “regeneration time” such that: 4$\begin{array}{cc}\frac{d{V}_{\mathrm{out}}\left(t\right)}{dt}=\frac{V_{\mathrm{out}}\left(t\right)}{\tau }& \left(6\right)\end{array}$

[0049] until the voltages on the outputs Out+ and Out− both reach one of the two predetermined “0” and “1” voltage output logic levels. FIG. 5d is a timing diagrams for comparator in accordance with the embodiment of FIG. 5b showing the state each stage is in during the clock signal TC and the delayed claock signal TC+TE.

[0050] Each latch's regeneration time constant τ depends upon the gain of the transistors Q5 and Q6. However, the gain of transistors Q5 and Q6 varies during each latch cycle as a function of the value of the latch's output voltage Vout. Nonetheless, τ does remain approximately constant during the initial part of each latch cycle when the latch's output voltage Vout has a small value relative to the latch's thermal voltage kT/q(Vout<<kT/q), where k is Boltzman's constant, T is absolute temperature, and q is the electron charge. This small-signal transistor model provides an approximate value for τ, using the tail current (Il) and the load capacitance CL on the complementary outputs Out+ and Out− including the collector-base capacitances of Q3-Q6: 5$\tau =\frac{4k{\mathrm{TC}}_L}{{\mathrm{qI}}_l}$

[0051] so that:

V out (t)=Vout(0)exp(t/τ).  (7)

[0052] Thus, although by the end of the regeneration phase τ is actually no longer a constant value, the exponential regeneration model using the small-signal assumption Vout(t)<<kT/q provides a constant value for τ that can be used to represent the latch's metastability performance, even so. Consequently, in FIGS. 3a, 3b and 4, the relationships between Pmeta, Tq and the SNR performance of a CT-DSM can be conveniently quantified by using multiples of this regeneration time constant τ as the measure of metastability.

[0053] In FIG. 5b, the comparator 10 preferably comprises a series of three of the D-type latch circuits shown in FIG. 5a and an unclocked buffer amplifier on the comparator's output (not shown) that assures an adequate output slew rate to prevent distortion. The second latch 22 of the comparator 10 is enabled by a delayed clock signal having a lag time TL. The delayed clock signal is produced by supplying the clock signal that enabled the first latch stage 20 to the second latch stage 22 through a delay device 28 that adds a delay TE, such that lag time TL=TE and Tc/2 >TE>0.

[0054] TE is selected so that the level of the signal output by the first latch 20 has enough time to regenerate out of the grey area before it is sampled by the second latch 22. In this way, the second latch 22 censors the output of the first latch 20, so that while the output of the first latch 20 is in an indeterminate transparent state, the signal output by the first latch 20 is not “seen” by the second latch 22. In practice, adequate delay TE is added to bring the SNR of the comparator to an acceptable level and, typically, Tc/2>>TE.

[0055] The third latch stage 24, in FIG. 5b, is enabled by the logical complement of the delayed clock signal that enabled the second latch stage 22 by simply swapping the respective delayed clock signals Tc+ and Tc− provided to the inputs of second stage 22 when that delayed clock signal is supplied to the third stage 24. Thus the lag time of this inverted delayed clock signal Ts relative to the clock signal enabling the first latch stage 20 is the sum Ts=TL+Tc/2 where TL=TE.

[0056] FIG. 5 c shows a comparator 10 for use in a CT-DSM in accordance with another preferred embodiment of the present invention. In this embodiment, the third latch 24 serves as an output buffer stage. All three latch stages 20, 22, 24, are preferably D-type latch circuits, preferably as shown in FIG. 5a. The second latch 22 is enabled by the logical complement of the clock signal that enables the first latch stage 20 by swapping the signals provided to the Tc+ and Tc− inputs of the second stage 22. Thus the second latch stage 22 is enabled by a clock signal having a lag time TL relative to the said given clock signal such that TL=Tc/2.

[0057] In FIG. 5c, the sample V(ti) of the analog input signal V(t) from the filter circuit 12 produced by the first latch stage 20 provides a leading edge for the comparator's output signal Sn. Because an inverted clock signal is supplied to the second stage 22, second stage 22 holds the leading edge value produced by the first latch stage 20 constant while the first latch stage 20 is in the transparent phase of its next latch cycle, i.e., while it is no longer producing a valid logic level. Of course, the first stage 20 then produces a valid logic level while the second stage 22 is in its transparent phase. Thus the regeneration phase of this second latch stage 22 holds the bit (bk) output by the comparator at a valid logic level while the first latch stage 20 is in a transparent phase and is not necessarily providing a valid logic level.

[0058] In FIG. 5c, the third latch stage 24, however, is enabled by the same clock that enabled the second latch stage 22, with an additional delay TE provided by a delay device 28 such that Tc/2>TE>0. This second lag time TS=Tc/2+TE is such that the third latch stage 24 enters its transparent phase only after the first latch stage 20 is already in its regeneration phase, and enters its regeneration phase while the second stage 22 is still in its regeneration phase. This lagged action of the third latch 24, the output buffer stage, censors any tendency of the comparator output to deviate from valid logic states during phase transitions in the first two latch stages 20 and 22. This eliminates the occurrence of “grey-area” low-voltage signals, that are not valid logic levels, in the early portion of each latch cycle for all but the first latch stage 20. Eliminating the occurrence of “grey area” input voltages at the inputs of these two latch stages, in this way, prevents the occurrence of metastable states at their outputs. However, in a small number of instances where the input signal V(t) is very small, the second latch stage 22 may be transparent and the output of the first latch stage 20 will not have finished regenerating when the third latch stage 24 becomes transparent, which may produce a metastable state in the bit stream (bk) output by the comparator that is the signal Sn input to the output interface 14.

[0059] FIG. 5 e is a timing diagram for comparator in accordance with the embodiment of FIG. 5c showing the state each stage 20, 22, 24 is in during the clock signal TC and the delayed clock signal TC+TE.

[0060] In both embodiments, because the metastability performance of the comparator shown therein depends primarily on the regeneration time required by the first latch stage 20, the designer can apply all available resources to the task of optimizing that one stage. For example, modified circuit topologies can be used to reduce parasitic capacitances that affect the regenerating nodes, and more supply current may be allocated to this one latch stage in each comparator, as is well known in the art.

[0061] The purpose of the second latch stage 22, in both embodiments of FIGS. 5b and 5c, is to hold the full voltage level for a binary “1” or “0” while both the other latch stages are transparent. The first and third stages are only both transparent for a period equal to TE or Tc/2−TE, respectively. However, the quantization latency is Tq=2(TE)+Tc/2 or Tq=2(Tc/2)+TE, respectively, and where TE<<Tc/2, the embodiment of FIG. 5b produces less quantization latency for better high frequency performance.

[0062] The Effect of Metastability on Continuous-Time Modulators

[0063] Because of the analog continuous-time, continuous-valued nature of the inputs to the comparators used in CT-DSMs, not all metastable states affect the SNR of CT-DSMs to the same extent. Metastable states of longer duration cause more degradation of the SNR. Thus, the extent of the SNR degradation of the signal output by a modulator is also affected by the waveform output by the comparator. As such, a more detailed analysis of comparator metastability would be useful to predict its effect on the SNR of CT-DSMs.

[0064] The four steps shown in FIG. 5f, model the over-all sampling, regenerating, limiting and censoring functions of the embodiment shown in FIG. 5d. In the first block 30, an ideal first latch stage samples the input voltage at a time nTc−To that is offset from the clock period by the sample offset interval To. The sampling instant nTc−To is defined as the time when the input signal most strongly correlates with the comparator output, and is determined statistically. Thus defined, the sampling instant may occur either before or after the beginning of the clock period Tc, depending on the device parameters in that critical first stage. The sampled value is then held constant over the remainder of the clock period until (n+1)Tc.

[0065] The second block 32 of FIG. 5f represents the exponential regeneration of the sampled signal by positive feedback by the cross-coupled pair within the first latch stage 20, as described above with reference to FIG. 5a. In the third block 34, regeneration terminates at the appropriate output voltage logic level (preferably 250 to 500 mV logic levels are implemented). The fourth block 36 represents the censoring function of the third latch stage 24 discussed above.

[0066] The continuous-time, continuous-valued comparator model shown in FIG. 5f can be used to determine the distribution of output voltages over time for a given distribution of input voltages using certain simplifying assumptions:

[0067] (1) Although τ actually increases as the magnitude of the output voltage Vout of the first latch stage increases, as noted above, τ has been treated as constant during the entire regeneration period, from the sampling instant to the time when a valid logic level is obtained on the output.

[0068] (2) Several other significant effects that occur in actual comparators have also not been accounted for: hysteresis, high-frequency response roll-off, intersymbol interference, aperture jitter and thermal noise. However, the design considerations other than the small-signal assumptions used for evaluating τ do not affect of metastability analysis.

[0069] (3) For convenience in modeling, the censoring time TL−To has been set at a length of 15 τ.

[0070] (4) The holding function of the second latch stage 22 is subsumed in the second and third blocks and, since the holding function of the second latch stage is transparently incorporated into this model, the fourth stage of the model is enabled on the clock cycle Tc rather than Tc/2.

[0071] In normal CT-DSM operating conditions (no overload) the spectrum of the signal V(t) that is provided by the filter circuit 12 to the comparators 10 is filtered so that samples of V(t) represented therein are correlated, and V(ti) has an approximately Gaussian distribution: 6$\begin{array}{cc}P\left[V_{\mathrm{out}}\left(t\right)\left|-1<V_{\mathrm{out}}\left(t\right)<+1\right|\right]\approx \frac{1}{{\sigma }_{\mathrm{in}}\exp \left(\frac{t-n{T}_c}{\tau }\right)\sqrt{2\pi }}& \left(8\right)\end{array}$

[0072] In the event that the limiter step 34 in the model shown in FIG. 5f is ineffective because neither limit value is attained: −1<Vout(t)<+1, then the input will have been amplified by at least a factor of 106 and, with a censoring period length of 15 τ, the output of the comparator will be proportional to the sampled input for a time (t) when t≧nTc+TLTo: 7$\begin{array}{cc}P\left[V_{\mathrm{out}}\left(t\right)|-1<V_{\mathrm{out}}\left(t\right)<+1\right]=\frac{1}{{\sigma }_{\mathrm{in}}\exp \left(\frac{t-{\mathrm{nT}}_c}{\tau }\right)\sqrt{2\pi }}\exp \left(-{\left[\frac{V_{\mathrm{out}}\left(t\right)}{{\sigma }_{\mathrm{in}}\exp \left(\frac{t-{\mathrm{nT}}_c}{\tau }\right)}\right]}^2\right)& \left(9\right)\end{array}$

[0073] The non-limited, proportional output Vout produced by (9) will have a Gaussian distribution with a larger variance than that produced by (8): 8$\begin{array}{cc}P\left[V_t\left({\mathrm{nT}}_c-T_o\right)\right]=\frac{1}{{\sigma }_{\mathrm{in}}\sqrt{2\pi }}\exp \left(-{\left[\frac{V_t\left({\mathrm{nT}}_c-T_o\right)}{{\sigma }_{\mathrm{in}}}\right]}^2\right)& \left(10\right)\end{array}$

[0074] The variance of the input signal, when scaled relative to the 250 to 500 mV digital swings typical of the output of these latches, is typically on the order of 10−2<sin<10−1. Since (10) applies only when −1<Vout(t)<+1, this results in: 9${\left[\frac{V_{\mathrm{out}}\left(t\right)}{{\sigma }_{\mathrm{in}}\exp \left(\frac{t-{\mathrm{nT}}_c}{\tau }\right)}\right]}^2<{10}^{-8}$

[0075] apparently indicating a negligible dependence of P[Vout(t)|−1<Vout(t)<+1|] on Vout(t). Given approximately uniform probability density of Vout(t) over the interval −1<Vout(t)<+1, therefore: 10$\begin{array}{cc}{V}_{\mathrm{out}}=\exp \left(\frac{t-{\mathrm{nT}}_c}{\tau }\right)V_t\left({\mathrm{nT}}_c-T_o\right)& \left(11\right)\end{array}$

[0076] As a description of the interval where metastability occurs (−1<Vout(t)<+1), the relative difference between (10) and (11) is less the 10−8. In this open interval, −1<Vout(t)<+1, the output values for any two different cycles Vout(t1), Vout (t2) are approximately conditionally independent of the input level Vin(ti) provided by the signal V(t) the filter circuit 12. Most of the probability distribution of Vout(t) is either P[Vout(t)=+1] or P[Vout(t)=−1] and is not independent of the input level Vti of Vt. Nonetheless, it is believed that equation #11 is a useful definition of latch behavior in the critical grey area −1<Vout(t)<+1 that approximates the metastability performance of the latch circuits in CT-DSMs.

[0077] Distribution of Output Trajectories in Simulations

[0078] FIGS. 6 and 7 show the results of SPICE time-domain transient response simulations demonstrating the improvement in metastability performance represented by that model of metastability performance that is achieved by comparators in accordance with the present invention. In these simulations, over 13.5 k sampling cycles were carried out at a 1.35 Ghz clock rate. The input signal sampled was the sum of 219 MHz and 311 MHz sine waves, an input selected to provide a full range of the possible combinations of amplitude and slew rate.

[0079] The metastability errors produced by a conventional, two-stage comparator (n=2), shown in FIG. 6, resulted in an SNR that calculated out at less than 47 dB. However, if another latch stage were added to the comparator (n=3), the resulting conventional, three-stage comparator would then have a quantization latency Tq=550 picoseconds that limits the modulator to operating frequencies below fmax=5 MHz. In contrast, using comparators that provide improved quantization in accordance with the present invention, a modulator can be satisfactorily operated above fmax=5 Mhz, up to 2 GHz at a SNR>55 dB.

[0080] Specifically, in accordance with the embodiment shown in FIG. 5b, a delay time (TE) selected such that 0<TE<Tc/2 is added to the clocks applied to the second and third stages in each comparator used in the delta-sigma modulator. The quantization latency Tq and metastability error probability Pmeta for these comparators then become:

T q =a+T E +T c (n−3)/2  (12)

P meta =b exp(−c[a+TE+Tc(n−3)/2])  (13)

[0081] In the simulations, that delay time (TE) of 110 picoseconds was added to the clock used in the simulation shown in FIG. 6, in accordance with the embodiment shown in FIG. 5b. The improved metastability performance thus produced, shown in FIG. 7, was obtained without the sacrifice of high frequency performance.

[0082] Transient Response Trajectories

[0083] In the transient response simulations shown in FIGS. 6 and 7, each output produced in response to an input sample is recorded as an individual “x” and those symbols collectively form “eye chart” scatter diagrams. The horizontal axis represents the time distribution of the outputs that were produced in response to the 13.5 k test samples sampled at times ti, in relation to one quantization cycle time period. The vertical position of each output is determined by its respective voltage level Vout(ti). The trajectories formed within these scatter diagrams provide a qualitative comparison of the noise occurring in the two respective comparator outputs.

[0084] In FIG. 6 the measurements are clearly more widely dispersed, which indicates the occurrence of a large number of metastable states. In contrast, almost all the 13.5 k response trajectories in FIG. 7 are tightly packed into a single narrow band, showing very little signal dependence. Only three trajectories showing significant metastability are visible, trajectories that separate from the narrow bands of trajectories corresponding to the normal response of a quantizer to the variable sample level and slew rate of the input waveform. Since the quantization cycle at the 1.35 Ghz clock rate is shorter than that used in some applications, this is a strenuous test of metastability. Therefore the test results indicate that the present invention affords substantial improvement for a range of DSM applications.

[0085] Estimated DSM SNR Attributable to Metastability

[0086] The achievable signal-to-noise ratio for a DSM device is limited by several other inherent sources of noise in addition to metastability, including quantization noise, thermal noise, and clock jitter. However, for the sake of comparison, an estimate of the signal-to-noise ratio that a respective DSM device using a respective type of comparator delta-sigma modulator would achieve in the absence of error sources other than metastability was calculated.

[0087] Ideally, each comparator 10 produces a binary output, which is one of two predetermined voltage levels with transitions between positive and negative polarity occurring only in predetermined time slots. This binary output is then converted by a digital to analog converter (DAC) into a charge that is injected back into the filter circuit 12. Ideal comparators would always provide full binary input levels to the DACs, such as the level seen in FIG. 2a. The full binary levels were −1.5 fC and +1.5 fC in this calculation. Distorted waveforms, produced by metastability errors in the comparators 10, such as the one seen in FIG. 2b, cause the DACs in the output interface circuit 14 to inject variable, that is, “non-binary” feedback charge values.

[0088] Where VT represents the thermal voltage (kT/q) and “tanh” indicates the hyperbolic tangent function the charge Idac produced by each DAC is Idac=tanh(Vout /VT) and the integral of the effective feedback charge Qi produced by the comparators in each cycle (i) can be defined as:

Q i =∫tanh(Vout(t)/VT)dt  (14)

[0089] This indefinite integral approximates the feedback charge provided by a DAC “buffer” gain stage in the output interface circuits following the comparator 10 in a DSM.

[0090] Using this feedback charge value (Qi) an estimated SNR can then be calculated from the mean and variance of the charge:

SNR= 10*log10[mean(Qi)/var(Qi)]  (15)

[0091] The estimated SNR contributed by metastability errors in the modulator simulation using a two-stage comparator is then 47 dB, and the estimated SNR produced in accordance with the present invention can be at a significantly improved 55 dB level in DSM devices that were the same except for the using comparator quantization in accordance with the present invention.

[0092] The invention has been described with reference to a presently preferred embodiment, but it will be apparent to one skilled in the art that variations and modifications are possible within the spirit and scope of the invention. As such, the invention is not to e limited to the disclosed embodiments except as required by the claims appended below.

Claims

1. A comparator having a signal input and a signal output, said comparator comprising: a first latch connected to the signal input, said first latch being adapted to be enabled to produce a first latch output signal in response to a signal on the signal input by a given clock signal having a given phase and a given cycle period Tc; delay means providing a delay TE such that Tc/2>TE>0; a second latch connected to said first latch and adapted to be enabled to produce a second latch output signal in response to a second latch input signal produced using said first latch output signal by a first delayed clock signal having a first lag time TL; and a third latch adapted to be enabled to supply a third latch signal to the signal output in response to said second latch output signal by a second delayed clock signal, said second delayed clock signal having a second lag time TS, said second delayed clock signal being provided to the third latch in cooperation with the delay means, such that TS=Tc/2+TE.

2. The comparator of claim 1 wherein first lag time TL=TE.

3. The comparator of claim 1 wherein first lag time TL=Tc/2.

4. The comparator of claim 1 wherein the delay TE<<Tc/2.

5. A modulator having a modulator input for receiving a given signal and a modulator output, said modulator comprising: a filter circuit connected to the modulator input, said filter circuit producing a filtered signal on a filter circuit output in response to the given signal; an output interface circuit, said output interface circuit being adapted to supply a signal to the modulator output, said filter circuit being adapted to use a signal produced by said output interface circuit to produce said filtered signal; a comparator adapted to connect said filter circuit output to an input of said output interface circuit; a first latch in said comparator, said first latch being connected to said filter circuit output and adapted to be enabled to produce a first latch output signal in response to said filtered signal by a given clock signal having a given phase and a given cycle period Tc; delay means in said comparator for providing a delay TE such that Tc/2>TE>0; a second latch in said comparator connected to said first latch and adapted to be enabled to produce a second latch output signal in response to a second latch input signal produced using said first latch output signal by a first delayed clock signal having a first lag time TL; and a third latch in said comparator adapted to be enabled to supply a third latch signal to the modulator output in response to said second latch output signal by a second delayed clock signal, said second delayed clock signal being provided to the third latch in cooperation with the delay means, such that TS=Tc/2+TE.

7. The modulator of claim 5 wherein first lag time TL=TE.

8. The modulator of claim 5 wherein first lag time TL=Tc/2.

9. The modulator of claim 5 wherein the delay TE<<Tc/2.

10. The modulator of claim 5, further comprising: a plurality of said comparators adapted to connect said filter circuit output to respective inputs of said output interface circuit, said output interface circuit being adapted to supply a quantized signal to the modulator output in response to the signals provided by the comparators to said output interface circuit; and threshold means for determining a respective signal threshold beyond which each of said comparators provides an output in response to said filtered signal from said filter circuit, said threshold means providing a different threshold to each of said comparators.

11. The modulator of claim 10, further comprising: a respective digital to analog converter connected to the output of each of said comparators, each converter being adapted to supply a respective feedback signal to said filter circuit.

12. The modulator of claim 5, wherein said filter circuit comprises a bandpass filter.

13. The modulator of claim 5, wherein said modulator over-samples an analog voltage input signal having a predetermined bandwidth and spectrum, said modulator producing a quantized binary output signal in response to said over-sampled analog voltage signal, said quantized binary output signal having a spectrum that is a sum of the input signal's spectrum, said modulator being programmable to shape a spectrum of the quantization noise in said quantized binary output signal, wherein said filter circuit comprises a programmable digital filter having a passband and a stopband, said passband being programmable for said predetermined bandwidth of said analog voltage input signal and said stop band being tunable to reject quantization noise; and wherein said comparator is a decimator, said decimator subsampling said digitally filtered binary output signal to generate an n-bit digital signal having a predetermined sampling frequency.

14. A method of quantizing a given input signal, said method comprising the steps of: supplying the given input signal to a first latch; enabling the first latch to produce a first latch output signal in response to said given input signal by providing a given clock signal having a given phase and a given cycle period Tc; supplying the first latch output signal to a second latch; enabling the second latch to produce a second latch output signal in response to said first latch output signal by providing a first delayed clock signal having a first lag time TL; supplying the second latch output signal to a third latch; and enabling said third latch to produce a third latch output signal in response to said second latch output signal by providing a delay TE so as to produce a second delayed clock signal having a second lag time TS such that TS=Tc/2+TE.

15. The method of claim 14 further comprising the step of delaying the given clock signal to produce the first delayed clock signal so that TL=TE.

16. The method of claim 14 further comprising the step of inverting the given clock signal to produce the first delayed clock signal so that TL=Tc/2.

17. The method of claim 14 wherein the delay TE<<Tc/2.

18. A method of producing a digital signal representing a given signal using a modulator having a filter circuit and an output interface, said method comprising the steps of: supplying a filtered signal produced in response to the given signal from the filter circuit to a first latch; enabling said first latch with a given clock signal having a given phase and a given clock cycle period Tc, so as to produce a first latch signal in response to the filtered signal; supplying a latch signal produced using the first latch signal to a second latch; enabling said second latch with a delayed clock signal to produce a second latch signal in response to said latch signal, said delayed clock signal having a lag time such that TL≠nTc/2 and TL≠0, where n is an integer; and supplying the second latch signal to the output interface, whereby transparency of the second latch stage to said first latch signal is reduced.

19. A comparator having a signal input and a signal output, said comparator comprising: a first latch connected to the signal input, said first latch being adapted to be enabled to produce a first latch output signal in response to a signal on the signal input by a given clock signal having a given phase and a given cycle period Tc; a second latch connected to said first latch and adapted to be enabled to produce a second latch output signal in response to a second latch input signal produced using said first latch output signal by a first delayed clock signal having a first lag time TL; and a third latch adapted to be enabled to supply a third latch signal to the signal output in response to said second latch output signal by a second delayed clock signal, said second delayed clock signal having a second lag time TS, said second delayed clock signal being provided to the third latch and where TS=Tc/2+TE and where Tc/2>TE>0.

20. The comparator of claim 19 wherein first lag time TL=TE.

21. The comparator of claim 19 wherein first lag time TL=Tc/2.

22. The comparator of claim 19 wherein the delay TE<<Tc/2.

23. A modulator having a modulator input for receiving a given signal and a modulator output, said modulator comprising: a filter circuit connected to the modulator input, said filter circuit producing a filtered signal on a filter circuit output in response to the given signal; an output interface circuit, said output interface circuit being adapted to supply a signal to the modulator output, said filter circuit being adapted to use a signal produced by said output interface circuit to produce said filtered signal; a comparator adapted to connect said filter circuit output to an input of said output interface circuit; a first latch in said comparator, said first latch being connected to said filter circuit output and adapted to be enabled to produce a first latch output signal in response to said filtered signal by a given clock signal having a given phase and a given cycle period Tc; a second latch in said comparator connected to said first latch and adapted to be enabled to produce a second latch output signal in response to a second latch input signal produced using said first latch output signal by a first delayed clock signal having a first lag time TL; and a third latch in said comparator adapted to be enabled to supply a third latch signal to the modulator output in response to said second latch output signal by a second delayed clock signal, said second delayed clock signal being provided to the third latch, where TS=Tc/2+TE.Tc/2+TE and such that Tc/2>TE>0.

24. The modulator of claim 23 wherein first lag time TL=TE.

25. The modulator of claim 23 wherein first lag time TL=Tc/2 such that the first delayed clock signal is a logical complemented of the given clock signal.

26. The modulator of claim 23 wherein the delay TE<<Tc/2.

27. The modulator of claim 23, further comprising: a plurality of said comparators adapted to connect said filter circuit output to respective inputs of said output interface circuit, said output interface circuit being adapted to supply a quantized signal to the modulator output in response to the signals provided by the comparators to said output interface circuit; and threshold means for determining a respective signal threshold beyond which each of said comparators provides an output in response to said filtered signal from said filter circuit, said threshold means providing a different threshold to each of said comparators.

28. The modulator of claim 27, further comprising: a respective digital to analog converter connected to the output of each of said comparators, each converter being adapted to supply a respective feedback signal to said filter circuit.

29. The modulator of claim 23, wherein said filter circuit comprises a bandpass filter.

30. The modulator of claim 23, wherein said modulator over-samples an analog voltage input signal having a predetermined bandwidth and spectrum, said modulator producing a quantized binary output signal in response to said over-sampled analog voltage signal, said quantized binary output signal having a spectrum that is a sum of the input signal's spectrum, said modulator being programmable to shape a spectrum of the quantization noise in said quantized binary output signal, wherein said filter circuit comprises a programmable digital filter having a passband and a stopband, said passband being programmable for said predetermined bandwidth of said analog voltage input signal and said stop band being tunable to reject quantization noise; and wherein said comparator is a decimator, said decimator subsampling said digitally filtered binary output signal to generate an n-bit digital signal having a predetermined sampling frequency.