BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a schematic diagram of a flash memory chip having an SPI in the prior art.
FIG. 2 illustrates a timing diagram of the flash memory chip shown in FIG. 1 when writing data.
FIG. 3 illustrates a flowchart of a process in accordance with an embodiment of the present invention.
FIG. 4 illustrates a schematic diagram of a flash memory chip having an SPI in accordance with an embodiment of the present invention.
FIG. 5 illustrates a timing diagram of the flash memory chip shown in FIG. 4 when writing data.
DETAILED DESCRIPTION
Please refer to FIG. 3, which illustrates a flowchart of a process 30 in accordance with an embodiment of the present invention. The process 30 is utilized for increasing transmission efficiency of an electronic device using an SPI, and includes following steps:
Step 300: start.
Step 302: receive data from a first pin of the SPI during a first duration according to a clock signal received from a clock pin of the SPI.
Step 304: output data from the first pin during a second duration according to the clock signal.
Step 306: end.
According to the process 30, the present invention can receive and output data through a pin of the SPI during different durations. That is, an identical pin can be used for receiving and outputting data at different time, so that transmission efficiency can be increased and wires can be decreased.
In the prior art, the SPI receives data through the serial data input pin and outputs data through the serial data output pin. In comparison, the present invention can uses the same pin of the SPI for receiving and outputting data at different time, so as to increase transmission efficiency.
Please refer to FIG. 4, which illustrates a schematic diagram of a flash memory chip 40 having an SPI in accordance with an embodiment of the present invention. The flash memory chip 40 includes a control circuit 400, a power pin VCC, a ground pin VSS, a serial data output pin Q′, a serial data input pin D′, a clock pin C′, a chip select pin S′, a hold control pin HOLD′, and a write protect pin W′. The control circuit 400 is designed according to the process 30. According to a clock signal received by the clock pin C′, the control circuit 400 receives data from a specified pin of the pins during a first duration, and outputs data from the specified pin during a second duration. In the flash memory chip 40, the power pin VCC and the ground pin VSS are coupled to a system power source and ground, the clock pin C′ receives the clock signal, and the chip select pin S′ indicates whether the flash memory chip 40 is deselected or not. Therefore, the power pin VCC, the ground pin VSS, the clock pin C′, and the chip select pin S′ cannot be used for exchanging data, while the serial data output pin Q′, the serial data input pin D′, the hold control pin HOLD′, and the write protect pin W′ can be used for exchanging data.
Please refer to FIG. 5, which illustrates a timing diagram of the flash memory chip 40 when writing data. In FIG. 5, from top to bottom are waveforms of the clock pin C′, the serial data input pin D′, the serial data output pin Q′, the hold control pin HOLD′, and the write protect pin W′. As shown in FIG. 5, during a duration T1, the flash memory chip 40 simultaneously receives data from the serial data input pin D′, the serial data output pin Q′, the hold control pin HOLD′, and the write protect pin W′, and during a duration T2 next to the duration T1, the flash memory chip 40 simultaneously outputs data from the serial data input pin D′, the serial data output pin Q′, the hold control pin HOLD′, and the write protect pin W′. Therefore, the efficiency and speed of data exchange in the flash memory chip 40 can be increased.
As mentioned above, the prior art SPI receives and outputs data in one way. Oppositely, the present invention can use an identical pin of the SPI to receive and output data in different time, so as to increase transmission efficiency.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Patent Application
20080005408
