This invention relates generally to the field of circuits for performing mathematical operations and more specifically to a method and apparatus for integer transformation using a discrete logarithm and modular factorization.
A k-bit integer n satisfying 0≦n≦2k−1 has a modular factorization n=|(−1)s2p3e|2
Known techniques for determining the exponent triple for a k-bit integer involve tables that grow exponentially with respect to k. These tables, however, are of limited use for representation of k-bit integers for k≧16. Accordingly, these known techniques are not efficient in certain situations.
According to one embodiment of the present invention, transforming an integer comprises receiving the integer, where the integer can be expressed as a modular factorization. The modular factorization comprises one or more factors, where each factor has an exponent. The integer is expressed as a product of residues. A discrete logarithm of the integer is established from a sum corresponding to the product of residues. A value for an exponent of a factor is determined from the discrete logarithm. The integer is represented as the modular factorization comprising the one or more factors, where each factor has a value for the exponent.
Certain embodiments of the invention may provide one or more technical advantages. A technical advantage of one embodiment may be that the exponent triple for a k-bit integer may be determined in a manner scalable with respect to k. Moreover, the exponent triple may be efficiently determined for k≧16, such as k=32, 64, or 128.
Certain embodiments of the invention may include none, some, or all of the above technical advantages. One or more other technical advantages may be readily apparent to one skilled in the art from the figures, descriptions, and claims included herein.
For a more complete understanding of the present invention and its features and advantages, reference is now made to the following description, taken in conjunction with the accompanying drawings, in which:
Embodiments of the present invention and its advantages are best understood by referring to
According to one embodiment, for 0≦n≦2k−1, p may be determined using a right-shift normalization step, and s may be determined by conditional complementation to obtain a normalized n congruent to 1 or 3 (mod 8). Transformation may then be reduced to determination of the discrete log e=dlg(n) for n congruent to 1 or 3 (mod 8), with 0≦e≦2k−2−1. According to the embodiment, the inverse transformation may then be reduced to evaluating the exponential residue operation to determine |3e|2
According to one embodiment, integers n that can be expressed as a product of residues may be identified, and the corresponding unique set of two-ones residues may be determined. In one embodiment, the set of two-ones residues may be given by {(2i+1)1≦i≦k−1, i≠2}, and a k-bit odd integer n congruent to 1 or 3 modulo 8 can be expressed as a product of a unique subset of these two-ones residues. For the remaining odd residues corresponding to n congruent with 5 or 7 modulo 8, the additive inverses |−n|2
According to one embodiment, the method transforms an odd k-bit integer n=αk−1αk−2 . . . α2α1α0 to the discrete log of n expressed as (s, e), where n=|(−1)s3e|2
For purposes of illustration, an example of the method is provided by lines LT1 though LT15 below:
Stimulus: k, n=αk−1αk−2 . . . α2α1α0, where α0=1.
Response: discrete log of n, expressed as (s, e), where n=|(−1)s3e|2
Referring to lines LT1 though LT15 and
If n can be expressed as a two-ones residue product, then the sign may be considered. For example, if n is not congruent with 1 or 3 modulo 8, that is, α2=1, then s may be set to s:=1 (as illustrated at lines LT2-LT3). The discrete log of the complement |2k−n|2
Variable e′ is updated at step 126. For pi=1, where pi represents the ith bit of P, variable e′ may be updated by subtracting the corresponding values dlg(2i+1) (which may be obtained from a table) from variable e′. For example, variable e′ may be updated according to e′=|e′−dlg(2i+1)|2
There may be a next bit to process at step 134. If there is a next bit, the method returns to step 126 to update variable e′ for the next bit. If there is no next bit, the method proceeds to step 140.
The result is calculated at step 140. The result may comprise (s, e) (as illustrated at line LT15). The result is provided at step 144. After providing the result, the method ends.
Modifications, additions, or omissions may be made to the method without departing from the scope of the invention. The method may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order without departing from the scope of the invention.
Modifications, additions, or omissions may be made to the TABLE 1 without departing from the scope of the invention. For example, TABLE 1 may be determined for the discrete logarithmic base g=|3i|2
For purposes of illustration, an example of the method is provided by lines LIT1 though LIT15 below. In the example, bit index i denotes a bit of the standard binary representation.
Stimulus: k, e=ek−3ek−4 . . . e2e1e0.
Response: |3e|2
Referring to lines LIT1 though LIT11 and
Variable e′ is updated at step 226. Variable e′ may be updated by subtracting the corresponding values dlg(2i+2+1) from variable e′. For example, variable e′ may be updated according to e′:=|e′−dlg(2i+2+1)|2
There may be a next bit to process at step 234. If there is a next bit, the method returns to step 226 to update variable e′ for the next bit. If there is no next bit, the method proceeds to step 240.
The result is calculated at step 240. The result may comprise P. After (k−2) steps, e′ becomes 0 and P corresponds to |3e−0|2
Modifications, additions, or omissions may be made to the method without departing from the scope of the invention. The method may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order without departing from the scope of the invention.
According to one embodiment, the exponent triple (s,p,e) for a k-bit integer n may be stored as a k-bit string using variable width fields. For 0≦n≦2k−1, the value of p determined by the right-shift normalization satisfies 0≦p≦k−1. Value p may be represented by the (p+1)-bit value 2p right adjusted in the k-bit field. For 0≦p≦2k−2, exponent e satisfies 0≦e≦2k−p−2−1. Exponent e may be stored in a (k−p−2)-bit field left adjusted in the k-bit field.
According to the embodiment, the lengths of the fields for e and 2p may be variable. In the embodiment, the lengths of the fields for e and 2p may total (k−1) bits, where a bit between the fields for e and 2p may provide sign bit information. For example, the bit between the fields may be assigned the value (e0 xor s). Accordingly, the length of the e field may be longer and the 2p field may be shorter when more bits are needed to store entries of the e field than to store entries of the 2p field. The length of the 2p field may be longer and the e field may be shorter when more bits are needed to store entries of the 2p field than to store entries of the e field.
According to one embodiment, the one-to-one mapping between 5-bit discrete log numbers comprising a 5-bit discrete log representations and 5-bit integers may be given by TABLE 2.
Modifications, additions, or omissions may be made to TABLE 2 without departing from the scope of the invention. TABLE 2 may include more, fewer, or other fields or entries.
A memory may store information. A memory may comprise one or more of any of the following: a Random Access Memory (RAM), a Read Only Memory (ROM), a magnetic disk, a Compact Disk (CD), a Digital Video Disk (DVD), a media storage, any other suitable information storage medium, or any suitable combination of any of the preceding.
Logic may process information for the component by receiving input and processing the input to generate output from the input. Logic may include hardware, software, other logic, or any suitable combination of any of the preceding. Certain logic, such as a processor, may manage the operation of a component. Examples of a processor may include one or more computers, one or more microprocessors, one or more applications, other logic operable to manage the operation of a component, or any suitable combination of any of the preceding.
According to the illustrated embodiment, transformation unit 10 is coupled to fields 40 storing values for exponents e, s, and p as illustrated. Transformation unit 10 includes a normalization portion 20, a sign portion 24, a conditional complement portion 28, and a DLG portion 32 coupled as illustrated. According to the embodiment, normalization portion 20 detects whether the operand is even or odd. If the integer is even, p may be established from the truncated trailing zeros. The number of trailing zeros represents the 2p factor. The value of p may also be used as a left-shift amount for the adjustment of the final result in the inverse transformation unit.
Sign portion 24 and conditional complement portion 28 detect the sign bit to establish s. The sign bit may be the third Least Significant Bit (LSB) of the normalized operand. If the sign bit is asserted, conditional complement portion 28 may complement the normalized operand by the input operand. DLG portion 32 accepts the complemented operand and calculates the discrete logarithm to yield e. DLG portion 32 may comprise a shifter and adder circuit and a read-only memory (ROM) lookup table as illustrated in
Modifications, additions, or omissions may be made to transformation unit 10 without departing from the scope of the invention. The components of transformation unit 10 may be integrated or separated according to particular needs. Moreover, the operations of transformation unit 10 may be performed by more, fewer, or other modules. Additionally, operations of transformation unit 10 may be performed using any suitable logic.
Initialization portion 60 performs initialization procedures, for example, according to lines LIT1-LIT4. Exponentiation portion 64 calculates exponentiation, for example, for example, according to lines LIT5-LIT10. According to one embodiment, portions 60 and 64 may be based on shift-and-add modulo 2k operations and may share resources.
Modifications, additions, or omissions may be made to inverse transformation unit 50 without departing from the scope of the invention. The components of inverse transformation unit 50 may be integrated or separated according to particular needs. Moreover, the operations of inverse transformation unit 50 may be performed by more, fewer, or other modules. Additionally, operations of inverse transformation unit 50 may be performed using any suitable logic.
Modifications, additions, or omissions may be made to circuit 90 without departing from the scope of the invention. The components of circuit 90 may be integrated or separated according to particular needs. Moreover, the operations of circuit 90 may be performed by more, fewer, or other modules. Additionally, operations of circuit 90 may be performed using any suitable logic.
Although this disclosure has been described in terms of certain embodiments and generally associated methods, alterations and permutations of the embodiments and methods will be apparent to those skilled in the art. Accordingly, the above description of example embodiments does not constrain this disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of this disclosure, as defined by the following claims.
This application claims benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application Ser. No. 60/721,559, entitled “Method And Apparatus For Integer Conversion Using The Discrete Logarithm And Modular Factorization,” Attorney's Docket 021791.0123, filed Sep. 27, 2005, by Alexandru Fit-Florea, et al.
Number | Date | Country | |
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60721559 | Sep 2005 | US |