Patent Application
20140117958
The technical field of the disclosure relates to voltage regulators and, more particularly, to low dropout (LDO) regulators.
An LDO regulator is a direct current (DC) linear voltage regulator that can operate with a very low dropout, where “dropout” (also termed “dropout voltage”) means the difference between the input voltage (e.g., received power supply rail voltage) and the regulated out voltage. As known in the conventional voltage regulator arts, low dropout voltage may provide, for example, higher efficiency and concomitant reduction in heat generation, and may provide for lower minimum operating voltage.
Two of the performance metrics for LDO regulators are the capability to avoid voltage drop, or “droop” in response to rapid load increase, and stability against oscillation. Conventional LDO regulators, though, are feedback devices. Therefore, as can be inherent in feedback devices, conventional design techniques directed to improving one of these two LDO regulator performance metrics may have opposite effects on the other. A completed conventional design of an LDO regulator may, therefore, reflect a compromise. One result of such conventional design compromise can be reduction in a maximum current capability, or current change, that the LDO regulator can handle while maintaining an acceptable droop. In addition, the compromise is embodied in fixed device parameters, for example fixed bias current and compensation components. However, operating conditions are not necessarily fixed. For example, LDO regulator output current may vary over a large range. One set of bias current or component values may be unable to provide optimal droop, or stability performance, or either, over the entirety of such a range.
The following summary is not an extensive overview of all contemplated aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.
One example adaptive low dropout (LDO) regulator in accordance with one or more exemplary embodiments may include a pass gate having a control input, and configured to provide a variable resistance current path from an external power rail to a pass gate output, at a resistance based, at least in part, on a pass gate control signal received at the control input, in combination with a load-based bias controller circuit configured to generate a load-based bias control signal corresponding, at least in part, to a load current that is output from the pass gate output. One example, further to one or more exemplary embodiments may also include an adaptive bias differential amplifier having a first input coupled to the pass gate output, a second input, and a transistor having a gate coupled to one of the first input and the second input. In an aspect, the adaptive bias differential amplifier may be configured to receive the load-based bias control signal and to bias the transistor at a bias level that may be based, at least in part, on the load-based bias control signal. In a further aspect, the adaptive bias differential amplifier may be configured to generate the pass gate control signal based on voltages received on the first input and the second input, according to a loop bandwidth based, at least in part, on the bias level.
In an aspect, the adaptive bias differential amplifier may further include an adaptive tail current source configured to receive the load-based bias control signal and, in response, pass a bias current through the transistor that is based, at least in part, on the load-based bias control signal, to bias the transistor at said bias level.
In one example adaptive LDO regulator in accordance with one or more exemplary embodiments, load-based bias controller circuit may be further configured to generate a load-based compensation control signal based, at least in part, on the load current. In an aspect, the adaptive LDO regulator may further comprise an adaptive compensation network coupled between the pass gate output and the adaptive bias differential amplifier. The adaptive compensation network may, accordingly, provide at least one zero in a transfer characteristic and, in an aspect, adaptive compensation network may be configured to receive the load-based compensation control signal and, in response, to adjust a position of the at least one zero.
In one example adaptive LDO regulator in accordance with one or more exemplary embodiments, the load-based bias controller circuit may be configured to transition a present state between a first state and a second state according to a hysteresis rule, and may be configured to generate the load-based bias control signal at a first bias control level when in the first state and to generate the load-based bias control signal at a second bias control level when in the second state. In an aspect, the hysteresis rule may comprise: when the present state is the first state, to transition the present state to the second state in response to the load current exceeding a first threshold, and when the present state is the second state, to transition the present state to the first state in response to the load current falling below a second threshold and, further to this aspect, the second threshold may be less than the first threshold.
In one example adaptive LDO regulator in accordance with one or more alternative exemplary embodiments, the load-based bias controller circuit may includes a two-state current mirror configured to receive a hysteresis control signal having a light load state value and a heavy load state value, and to receive the pass gate control signal. In an aspect, the a two-state current mirror may be configured while the hysteresis control signal is at the light load state value, to pass a sense current at a first scalar multiple of the pass gate control signal, and while the hysteresis control signal is at the heavy load state value, to pass the sense current at a second scalar multiple of the pass gate control signal, wherein the second scalar multiple is greater than the first scalar multiple.
In an aspect, a current-to-voltage detector may be coupled to the two-state current mirror and may be configured to generate the hysteresis control signal, and the current-to-voltage detector may be configured to generate the hysteresis control signal at the light load state value in response to the sense current being less than a given sense current threshold and to generate the hysteresis control signal at the heavy load state value in response to the sense current being greater than the given sense current threshold.
In a further aspect, the load-based bias controller circuit may be configured to generate the load-based bias control signal based, at least in part, on the hysteresis control signal.
One or more exemplary embodiments provide methods for controlling a low dropout (LDO) regulator having a pass gate output and having a transistor-based differential amplifier that is configured to control a voltage-controlled pass gate to pass a load current from a power rail to the pass gate output, and examples of such methods can include generating a bias control signal indicative of a characteristic of the load current, and biasing the transistor-based differential amplifier at a level based, at least in part, on the bias control signal.
In an aspect, generating the bias control signal may include generating the bias control signal at a first bias control level in response to the load current exceeding a load threshold, and generating the bias control signal at a second bias control level in response to the load current not exceeding the load threshold.
In another aspect, generating the bias control signal may include setting a present generating state to one from among a first generating state and a second generating state, generating the bias control signal according to the present generating state until an occurrence of a transition event, wherein the transition event may be defined by a hysteresis transitioning rule and, upon the transition event, transitioning to a next generating state, making the next generating state the present generating state, and returning to the generating the bias control signal according to the present generating state.
In a related aspect, a hysteresis transitioning rule may include, for example, when the present generating state is the first generating state, the transition event being the load current exceeding a first threshold, and when the present generating state is the second generating state, the transition event being the load current not exceeding a second threshold, and in a further aspect the second threshold may be less than the first threshold.
One or more exemplary embodiments may provide an LDO regulator having a pass gate having a control input, and configured to provide a variable resistance current path from an external power rail to a pass gate output, at a resistance based, at least in part, on a pass gate control signal received at the control input, a differential amplifier having a first input coupled to the pass gate output, a second input, and a transistor having a gate coupled to one of the first input and the second input, wherein the bias differential amplifier is configured to generate the pass gate control signal based on voltages received on the first input and the second input, in combination with means for adapting a bias of the transistor according to a load current output from the pass gate output, and the differential amplifier may be configured to generate the pass gate control signal according to a loop bandwidth based, at least in part, on the bias of the transistor.
The accompanying drawings found in the attachments are presented to aid in the description of embodiments of the invention and are provided solely for illustration of the embodiments and not limitation thereof.
Aspects of the invention are disclosed in the following description and related drawings directed to specific embodiments of the invention. Alternate embodiments may be devised without departing from the scope of the invention. Additionally, well-known elements of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term “embodiments of the invention” does not require that all embodiments of the invention include the discussed feature, advantage or mode of operation.
The terminology used herein is only for the purpose of describing particular examples according to embodiments, and is not intended to be limiting of embodiments of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein the terms “comprises”, “comprising,”, “includes” and/or “including” specify the presence of stated structural and functional features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other structural and functional feature, steps, operations, elements, components, and/or groups thereof.
The phrases “persons skilled in the art” and “those of skill in the art” have identical meaning, which is “persons of ordinary skill in the art to which the embodiments pertain,” and the phrases “a person skilled in the art” and “a person of skill in the art” have identical meaning, which is a “a person of ordinary skill in the art to which the embodiments pertain.”
Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields, electron spins particles, electrospins, or any combination thereof.
The term “topology” as used herein refers to interconnections of circuit components and, unless stated otherwise, indicates nothing of physical layout of the components or their physical locations relative to one another. Figures described or otherwise identified as showing a topology are no more than a graphical representation of the topology and do not necessarily describe anything regarding physical layout or relative locations of components.
The differential amplifier 102 may include, for example, two transistor-controlled branches (shown but not explicitly labeled), extending in parallel from a top common node 103 (which may be the Vdd rail) to a bottom common node 105. A fixed bias current source (alternatively referred to as “tail current source”) 106, described in greater detail later, sinks a bias current I5 from the bottom common node 105 to a sink or reference rail, e.g., the Vss power or reference rail.
One of the two transistor-controlled branches can be formed by a series coupling of a first transistor M2, alternatively referenced as the “feedback-controlled input transistor” M2, and a first load or first current source transistor M6. In one example, a first electrode (shown but not separately labeled) of M2 may couple to the bottom common node 105, and a second electrode (shown but not separately labeled) of M2 may couple, through M6, to the top common node 103. The gate (shown but not separately labeled) of M2 may couple to, or be integral with a first input (shown but not separately labeled) of the differential amplifier 102.
The other of the two transistor-controlled branches may be formed by a series coupling of a second transistor M4, alternatively referenced as the “reference-controlled input transistor” M4 and a second load or second current source transistor M5. In one example coupling, a first electrode (shown but not separately labeled) of M4 may couple to the bottom common node 105, and a second electrode (shown but not separately labeled) of M4 may couple through M5 to the top common node 103. The gate (shown but not separately labeled) of M4 may couple to, or be integral with a second input (shown but not separately labeled) of the differential amplifier 102.
For brevity in describing example operations, the reference input transistor M4 and the feedback input transistor are hereinafter alternatively referenced, collectively, as “input transistors M2 and M4.”
Transistors M3, M7, M8 and M10 form an intermediate buffer stage (shown but not separately numbered. The drain of M8 couples a pass gate control signal, or pass gate control voltage Vhg to the control input (shown but not separately numbered) of the output pass gate M9.
As previously described, the tail current source 106 sinks a bias current I5 from the bottom common node 105, and the magnitude of I5 sets the bias of the input transistors M2 and M4. The bias of the input transistors M2 and M4 affects the bandwidth and slew rate of the LDO regulator 100. The tail current source 106 is fixed, though, so the value of I5 is selected (e.g. the tail current source is fabricated) to bias the input transistors M2 and M4 at a value that may be based on optimal point with respect to bandwidth and slew rate. However, the value of I5 may have other effects; for example, a higher I5 can increase power loss. Accordingly, in various applications, selection of the value of I5 may embody compromises among, and of multiple performance goals of the LDO regulator 100.
Referring to
However, various complications may arise, for example, in selecting the positions of the zeros. One such complication is that the position of the poles may vary with respect to I_LOAD. Another complication, which may arise in particular when compensating against instabilities from intentionally placed poles, is that the compensation may operate counter to the improvement (e.g., certain transient response) for which the pole was selected. Accordingly, in various applications, selection of the target positions of the zeros, and therefore the values of components within the compensation network that set such positions, may embody compromises between, for example, transient response and stability of the LDO regulator 100.
The load-based bias controller 204 may be configured, in accordance with exemplary embodiments, to control the adaptive tail current source 206 by a load-based bias control signal ADP_BIAS, generated based on one or more characteristics of the load current I_LOAD. In a further aspect, the load-based bias controller 204 can generate ADP_BIAS to place transistors within the adaptive bias differential amplifier 202 at a bias level, i.e., an operating point dynamically adapted to the one or more characteristics of I_LOAD.
The load-based bias controller 204 may be configured to generate ADP_BIAS based on a present magnitude of I_LOAD. It will be understood that this is only one example of “based on” on I_LOAD and is not intended to limit the scope of practices contemplated by the exemplary embodiments. For example, as described in greater detail at later sections, generation of ADP_BIAS in accordance with one or more exemplary embodiments encompasses generation based on a present state of the load-based bias controller 204 and a transition event, e.g., a detected I_LOAD event that is defined, at least in part, according to the present state.
In another aspect, the adaptive bias and compensation LDO regulator 200 further includes, in accordance with one or more exemplary embodiments, an adaptive compensation network 208 coupled between the feedback path 220 and, for example, the pass gate control line 210. In a further aspect, the adaptive compensation network 208 may include variable, controllable elements, e.g., at least one voltage-controlled resistance element 208-1 and/or at least one variable capacitance element such as 208-2, also controlled based on I_LOAD. Control of the variable elements may be provided by a load-based compensation control signal, for example, ADP_CMP that may be generated by the load-based bias controller 204 based on I_LOAD. In an aspect, adaptive compensation network 208 responds to the ADP_CMP signals by varying one or more of its variable components, e.g., the variable resistance element 208-1, to adapt its transfer characteristic, e.g., a position of at least one zero, in accordance with I_LOAD. In one aspect, the load-based bias controller 204 may be configured to adjust or adapt the biasing of adaptive differential amplifier 202 using an I_LOAD verses bias level characteristic different from than used to adjust or adapt the adaptive compensation network 208.
The
It will be understood that the example load-based bias controller 204 is not intended to limit the scope of any exemplary embodiments. Embodiments contemplate generating ADP_BIAS and ADP_CMP based on I_LOAD according to any given mapping, for example, any mapping that can be represented as:
ADP_BIAS=ƒ(I_LOAD) Eq. (1)
ADP_CMP=g(I_LOAD) Eq. (2)
It will be understood that ƒ and g in Equations (1) are not intended to limit for g to being closed-form functions; one or both can be any mapping.
Referring to
“Level—1” and “Level—2” may be alternatively referenced as a “first bias control level” and a “second bias control level,” respectively. It will be understood that the form of Equation (3) is only an approximation of a two-stepped value of ADP_BIAS, which is just one generation of bias currents in practices according to the exemplary embodiments. Actual implementations of a two-stepped generation may generate ADP_BIAS in a manner that deviates from Eq. (3). For example, actual implementations of the comparators 218 may exhibit breakpoints that may vary from “THLD,” as well as deviating from the nominal relations of “less than or equal to” and “greater than” appearing in Equation (3).
It will be understood if ADP_BIAS is chosen as a discrete stepped generation the number of steps is not limited to two. On the contrary, two comparators 218 may be used, such that ADP_BIAS may be a mapping or function ƒ(I_LOAD) with ƒ being a multi-step value, e.g., a three-step function such as
or an equivalent form such as the following Equation (3A):
The values “THLD—1” and “THLD—2” are one example of, and can be referenced as a “first current threshold” and a “second current threshold,” respectively. The bias levels “Level_A” and “Level_B” can be another example of a “first bias control level” and a “second bias control level,” respectively. “Level_C” can be one example of, and can be referenced alternatively as a “third bias control level.” Regarding the arrangement of the comparators 218, representative examples are shown with a “−” input and a “+” input (collectively “+/−” inputs). One of the +/− inputs may be coupled to an input (shown but not separately numbered) of the load-based bias controller 204, to receive an I_LOAD detection signal, for example VLdet from the load current detector circuit 216. The other of the +/− inputs may be coupled to a reference such as the threshold voltage reference 212.
It will be understood that if more than one comparator 218 is used, e.g., two or more comparators 218 for ADP_BIAS and one or more comparators for ADP_CMP, the threshold voltage reference 212 may be configured to provide a different reference voltage (not separately shown) to each of the different comparators 218. Alternatively, the threshold voltage reference 212 may be configured to generate a single reference voltage, e.g., Vref, and the load-based bias controller 204 may be configured with circuitry (not shown) to generate different reference voltages for the different comparators 218.
With respect to specific technologies for the comparators 218 and the threshold voltage reference 212, each of these may be application-specific and each may be, at least in part, design choice. However, selection and implementation of the comparators 218 and the threshold voltage reference 212 may be readily performed by persons of ordinary skill, by applying conventional techniques known to such persons to the present disclosure, without undue experimentation. Further detailed description of such selection and implementation is therefore omitted.
With respect to specific means and technologies for the load current detector circuit 216 for generating VLdet, exemplary embodiments are not limited to any particular one of such means or technologies. For example, the load current detector circuit 216 may measure I_LOAD directly, e.g., as a direct current-to-voltage conversion (not explicitly shown in
Means for communicating the generated ADP_BIAS and ADP_COMP from the load-based bias controller 204 to the adaptive bias differential amplifier 202 (e.g., to the adaptive current source 206), and to the adaptive compensation network 208, respectively, may include a bias/compensation control line 230. In one aspect, the bias/compensation control line 230 may branch to a bias control line 230-1 coupled to the adaptive bias differential amplifier 202, and to a compensation control line 230-2 coupled to the adaptive compensation network 208. It will be understood that the term “line” in the label “bias/compensation control line” 230 encompasses “bus” and “channel.” It will be understood that “branch,” in the context of the “bias/compensation control line (or bus)” 230 does not necessarily require a physical branching. For example, embodiments contemplate the bias/compensation control line 230 being a common, or shared bus connecting the load-based bias controller 204 to the adaptive bias differential amplifier 202 and to the adaptive compensation network 208. It will be understood that the bias/compensation control line 230 may be, for example, a parallel N-bit bus or line, having one or more of its N bits allocated for ADP_BIAS, and one or more allocated for ADP_CMP. In another example alternative, the bias/compensation control line 230 may be configured as a serial stream, employing, for example, any known conventional technique for multiplexing serial bits. In another example alternative, the bias/compensation control line 230 may be configured to carry one or both of ADP_BIAS and ADP_CMP as an analog signal at a continuously variable level, at a given mapping to a continuously variable load current I_LOAD.
In an example configuration, the load-based bias controller 204 may have one comparator 218 for ADP_BIAS, and may have a threshold voltage reference 212 and a load current detector circuit 216. The load current detector circuit 216 may be configured to generate VLdet as a particular function or mapping of I_LOAD, such that I_LOAD equals a threshold, e.g., THLD, when VLdet is at a given load detection threshold. Likewise, the threshold voltage reference 212 and one comparator 218 can be configured such that when I_LOAD falls below THLD, VLdet falls below the load detection threshold, causing ADP_BIAS to change from Level—2 (e.g., a high load) to Level—1 (e.g., a light load). In response to this change in ADP_BIAS, the adaptive tail current source 206 may increase I_BIAS from a heavy load bias current to a light load bias current. The light load bias current biases the input transistors M2 and M4 at an operating point, i.e., a light load bias level, at which the loop bandwidth is higher than the loop bandwidth exhibited when biased, by the heavy load bias current, at a heavy load bias level. This described stepped-value in ADP_BIAS, provided by the
In the above-described example, when I_LOAD increases to a level exceeding THLD the comparator 218 switches again, such that ADP_BIAS changes from Level—1 (light load) back to Level—2 (heavy load). The adaptive tail current source 206 may, in response, switch OFF, or reduce I_BIAS to a lower default value, i.e., to the heavy load bias current. It will be understood that, in an aspect, provision for such switching OFF or reduction of I_BIAS may include the adaptive tail current source 206 being formed of two or more individually switchable (not explicitly shown) tail current sources in parallel. For example, the adaptive tail current source 206 may be formed of a nominal (not shown) tail current source and an “extra” or supplemental tail current source (not shown) that is selectively activated, by ADP_BIAS, for example in response to detecting light load conditions. Such switching OFF or reduction of I_BIAS may, in turn, drive the input transistors M2 and M4 to an operating point, e.g., to the heavy load bias level, at which the loop bandwidth is lower and therefore provide for better power efficiency.
The above-described examples of changing ADP_BIAS between Level—1 and Level—2 are an implementation of a mapping according to Equation (2), in which the light load bias level and the heavy load bias level can be characterized as a first bias level and a second bias level. One alternative embodiment can be a three-level load-based biasing, i.e., an implementation according to Equation (4) or (4A).
Referring to
With respect to technology for the variable resistance elements 208-1 and variable capacitor elements 208-2, these may be implemented by, for example, adapting known conventional voltage controlled resistor techniques, and known conventional voltage controlled capacitor techniques to the present disclosure. Further detailed description is therefore omitted.
The
For brevity, “hysteresis load threshold bias controller” 302 will be alternatively referred to as “HLT bias controller” 302. It will be understood that “HLT” has no intended additional meaning; it is simply an abbreviation for “hysteresis load threshold.” To avoid obfuscation of concepts, detailed description of the generation of the adaptive bias and compensation LDO regulator 300 and its HLT bias controller 302 will generally reference ADP_BIAS. Structure and operations specifically performed for generating ADP_CMP are generally omitted. It will understood, though, that the HLT bias controller 302 may be configured for generating ADP_CMP with structure and operation substantially identical to that described for generating ADP_BIAS. Likewise, as will appreciated by persons skilled in the art upon reading this disclosure, generation of ADP_BIAS and ADP_CMP may be provided, for example, using two (not explicitly shown) HLT bias controllers 302, configured to generate each with its own hysteresis rules.
According to various exemplary embodiments, the HLT bias controller 302 can be configured to have a first state, for example a light load state, and a second state, for example a heavy load state. The HLT bias controller 302 can be configured to generate the ADP_BIAS, the above-described load-based bias control signal, at a first bias control level, e.g., Level—1, when in the first state and to generate ADP_BIAS at a second bias control level, e.g., Level—2, when in the second state. In an aspect, the HLT bias controller 302 can be configured to transition back and forth between the first state and the second state according to a given hysteresis rule, examples of which are described in greater detail below
In one example according to one or more aspects, the HLT bias controller 302 may be configured with a two-state current mirror 350 having a current output (shown but not separately numbered) coupled to a sense node 304, and a threshold current source 306 coupling the sense node 304 to a reference rail, e.g., Vss. In an aspect, the threshold current source 306 can be configured to pass a current, termed hereinafter a “sense current” or I_SN, from the sense node 304 to the reference rail Vss at a low resistance if I_SN is less than a given sense current threshold, labeled I_THX, but transitions rapidly to a high resistance when I_SN reaches I_THX. The threshold current source 306 can be configured such that the resistance to an I_SN less than I_THX produces a sense voltage Vdet on the sense node 304 less than a given voltage threshold VTH, but rapidly increases above VTH upon I_SN current exceeding I_THX.
Referring to
In one aspect, subject to the limit of I_THX imposed by the threshold current source 306, the two-state current mirror 350 can be configured to pass I_SN to the sense node 304, when in its first current mirror state, as a first scalar multiple of the pass gate control signal Vhg. It will be understood that “scalar multiple” can be less than unity. For purposes of illustration, one example value of the first scalar multiple can be one-eighth. Since Vhg is proportional to I_LOAD, I_SN is proportional to (e.g., one eighth of) I_LOAD according to the first scalar multiple while the two-state current mirror 350 is in the first current mirror state, provided I_SN is less than I_THX. In a related aspect, still subject to I_THX, the two-state current mirror 350 can be configured to pass I_SN to the sense node 304, when in its second current mirror state, as a second scalar multiple of the pass gate control signal Vhg, with the second scalar multiple being greater than the first scalar multiple. For purposes of illustration, one example second scalar multiple can be one-fourth. In other words, according to this example (and assuming I_SN is less than I_THX), the two-state current mirror 350 in its second current mirror state passes to the sense node 304, in accordance with Vhg, a magnitude of I_SN that is twice the magnitude of I_SN that it passes in the first current mirror state.
As will be understood, the second scalar multiple being greater than the first scalar multiple can provide a transitioning of ADP_BIAS from a light load bias level to a heavy load bias level when I_LOAD exceeds a first threshold, but requires I_LOAD to fall to a second threshold that is less than the first threshold to transition ADP_BIAS back to the light load bias level. As an illustration, the second scalar multiple will be assumed as twice the first scalar multiple, and an assumed first threshold will be THLD. The ADP_BIAS levels will be assumed to be the previously described Level—1 and Level—2. Under these assumptions, the ADP_BIAS transitions from Level—1 to Level—2 when I_LOAD exceeds THLD but, in accordance with a hysteresis, requires I_LOAD to fall to one-half of THLD for ADP_BIAS to transition from Level—2 back to Level—1.
In overview, the HLT bias controller 302 may generate ADP_BIAS (and/or ADP_CMP, as described above) to transition the adaptive bias and compensation of LDO regulator 300 between multiple states, using transition rules that may depend in, in part, on its present state. One example configuration of the HLT bias controller 302 is described as having a first state and a second state in generating ADP_BIAS. In an aspect, the HLT bias controller 302 has a first I_LOAD threshold or transition event for switching from the first state to the second state and a second I_LOAD threshold or transition event for switching from the second state to the first state. In accordance with a hysteresis function, the first I_LOAD threshold may be higher than the second I_LOAD threshold. One example first state can be a “light load state” and a corresponding second state can be a “heavy load state.” As to specific values defining “light load” and “heavy load” in the context of the
For purposes of description, the I_LOAD transition event or threshold causing switching of the HLT bias controller 302 from the light load state to the heavy load state will be referred to as a first threshold, or “I_TH1.” One example I_TH1 may be the previously described THLD. The I_LOAD threshold or transition event causing switching from the heavy load state to the light load state will be referred to as a second threshold, or “I_TH2.” In accordance with a hysteresis feature, I_TH2 may be lower than I_TH1. As illustration, the HLT bias controller 302 may be configured such that I_TH2 is ½ I_TH1. As will be appreciated by persons of skill in the art having view of the present disclosure, setting I_TH2 at, for example. ½ I_TH1 may provide various advantages and benefits, for example, repeated switching between the light load state and heavy load state due to I_LOAD oscillating at one of the thresholds.
As previously described, the HLT bias controller 302 may include a two-state current mirror 350. In one example implementation of the two-state current mirror 350 may include a current mirror transistor M30 having its gate (shown but not separately numbered) coupled to the pass gate control line 210 to receive the pass gate control voltage Vhg. In one aspect, described in greater detail at later sections, the current mirror transistor M30 may be a PMOS scaled copy of the PMOS pass gate M9. The current mirror transistor M30 will therefore be referred to, alternatively, as the “scaled mirror transistor” M30. The source (shown but not separately numbered) of the scaled mirror transistor M30 may be coupled to the Vdd power rail. The drain (shown but not separately numbered) of the scaled mirror transistor M30 may be coupled to a sense node 304.
A switched current mirror device 352 comprising another current mirror transistor M32 in series with a switch transistor M34 provides a parallel path from Vdd to the sense node 304. The current mirror transistor M32 will be alternatively referenced as the “switched current mirror transistor” M32. The switched current mirror transistor M32 has a gate (shown but separately numbered) coupled, like the gate of the scaled mirror transistor M30, to the pass gate control line 210, and drain (shown but not separately numbered) coupled to the sense node 304. The switched current mirror device 352 differs from the current mirror transistor M30 because the source (shown but not separately numbered) of the switched current mirror transistor M32 is switchably coupled to the Vdd rail, by the switch transistor M34, instead of being directly coupled like the current mirror transistor M32. The switch transistor M34 may be controlled by a hysteresis control signal HYS, generated as described in greater detail later, to switch between a light load state and a heavy load state. In the
Referring to
As previously described, the threshold current source 306 is coupled between the sense node 304 and Vss. In an aspect, the threshold current source 306 may be configured with a current-to-voltage characteristic that effectively sources, i.e., passes, I_SN from the sense node 304 to Vss without substantial resistance—provided I_SB is less than I_THX. Further to this aspect, the threshold current source 306 can be configured to provide substantial resistance to a magnitude of I_SN greater than I_THX.
An inverting threshold detector 308 has an input (shown but not separately numbered) coupled to the sense node 304, and an output coupled to the gate of the switch transistor M34. The output of the inverting threshold detector 308 is the above-described hysteresis control signal HYS that couples to the gate (shown but not separately numbered) of the switching transistor M34 of the switched current mirror device 352. A previously described, the inverting threshold detector 308 has a switching threshold corresponding to VTH of the threshold current source 306. In an aspect, the HLT bias controller 302 may include a bias signal generating circuit or function, for example a series arrangement of the inverting threshold detector 308 and another buffer, such as the inverting buffer 310 for generating ADP_BIAS based on the state of the two-state current mirror 305.
It will be understood from the description above that when the two-state current mirror 350 is in its light load state, I_SN is less than I_THX and the current mirror transistor M30 is the only device supplying I_SN. However, upon I_LOAD exceeding a given I_TH1, e.g., above-described THLD, the pass gate control voltage Vhg causes the current mirror transistor M30 to pass a current greater than I_THX. Upon I_SN exceeding I_THX the current-voltage characteristic of the threshold current source 306 rapidly increases Vdet at the sense node 304 to a value exceeding VTH. The corresponding switching of the inverting threshold detector 308 switches HYS to a low value. The switching of HYS to the low value switches ON the switched current mirror device 352. This places the two-state current mirror 350 in the heavy load state. As will be appreciated from further detailed description, a result of the switched current mirror device 352 being in an ON state is that I_LOAD must be smaller than THLD before I_SN can fall below I_THX, i.e., where Vdet will be less than the VTH. For example, assuming the switched current mirror transistor M32 of the switched current mirror device 352 has the same current-voltage characteristic as the current mirror transistor M30, I_LOAD must fall to less than ½ THLD before I_SN will fall below I_THX. This provides the hysteresis feature of the HLT bias controller 302.
As previously described, in an aspect, for I_SN less than I_THX the current mirror transistor M30 may be configured to generate I_SN in scalar proportion, e.g., 1/K, to I_LOAD. Techniques for configuring the current mirror transistor M30 to generate I_SN as 1/K of I_LOAD are described in greater detail at later sections. For example, if K is eight I_SN will be ⅛ of I_LOAD and, therefore, the threshold current source 306 must be configured such that I_THX is ⅛ of THLD. Continuing with this example, another assumption is that the switched current mirror transistor M32 of the switched current mirror device 352 has the same current-voltage characteristic as the current mirror transistor M30. Therefore, upon I_SN exceeding I_THX, the above-described rapid increase of Vdet will cause HYS to go low, which switches on the switched current mirror device 352. This places the two-state current mirror 350 in the heavy load state. Absent the cut-off imposed by the threshold current source 306, the two-state current mirror 350 generates I_SN as ¼ of I_LD, instead of ⅛ of I_LOAD. However, the cut-off or saturation of the threshold current source 306 is ⅛ of THLD. Therefore, I_SN will not fall below I_THX until I_LD falls below ½ THLD.
Example operations of the HLT bias controller 302 in generating ADP_BIAS according to one illustrative hysteresis rule will be described in reference to
Referring to the
Referring to
In one example operation, the two-state current mirror 350 may be assumed to start in the light load state, i.e., I_SN less than I_THX. Vdet at the sense node 304 is therefore less than VT and, accordingly, the HYS output of the inverting threshold detector 308 is high. The switched current mirror device 352 is therefore OFF and the inverting buffer 310 generates ADP_BIAS at Level—1. Generation of ADP_CMP is not described, but may be assumed to be at a level corresponding to ADP_BIAS at Level—1. The current mirror transistor M30 varies I_SN as 1/K times I_LOAD and, since I_LOAD is less than THLD, I_SN is less than I_THX. When I_LOAD reaches THLD. I_SN reaches I_THX, the sharp cut-off of the threshold current source 306 causes Vdet on the sense node 304 to quickly rise above VTH. In response, the inverting threshold detector 308 output i.e., the hysteresis control signal HYS, switches to a low or logical “0” state. This, in turn, has two effects. One is the ADP_BIAS output from the inverter 310, switches to Level—2, which switches the adaptive tail current source 206 OFF, or reducing I_BIAS to a lower default value. The second is that the switch transistor M34 of the switchable current mirror device 352 switches ON, effectively doubling the current versus Vhg characteristic of the two-state current mirror 350. I_SN therefore remains slightly above I_THX, which continues to hold Vdet above VTH.
Continuing with the above-described example, assume I_LOAD decreases to a level slightly below THLD. If the current mirror transistor M30 were the only current mirror responding to Vhg, the sense current I_SN would fall below I_THX. However, since the two-state current mirror 350 is in the heavy load state, the switch transistor M34 is ON and both the current mirror transistor M30 and the switched current mirror transistor M32 are operative. Therefore, I_SN will not fall below I_THX until I_LOAD is less than one-half of THLD. Assuming I_LOAD eventually decreases to slightly lower than one-half of THLD, the corresponding lowering of I_SN to less than I_THX causes Vdet to fall below VTH. The inverting threshold detector 308 will then switch HYS to a high state, which places the two-state current mirror 350 back to the light load state.
Example aspects of structure and arrangement of the transistors M30, M32 and M34 will now be described in greater detail.
In an aspect, M30 and M9 may have substantially the same structure except for M30 having a channel width (not explicitly shown) that is a fractional portion, for example, 1/K, of the M9 channel width (not explicitly shown). It will be understood by persons of skill in the art that K may be unity, but a result may be significant power loss in the HLT bias controller 302. As previously described, one example value of K is eight. For this value of K the channel width of M30 can be ⅛ the channel width of the pass gate M9. This is only an example, not intended to limit the scope of any exemplary embodiment.
In an aspect, the channel widths of M32 and M34 may be identical to the channel width of M30. As will be appreciated by persons skilled in the art upon reading this entire disclosure, this example relation of the channel widths of M30, M32 and M34 may provide I_TH2 as ½ I_TH1. As will also be appreciated, the proportional relationships of the channel widths of M30, M32 and M34 may be varied to provide correspondingly different proportional relationships of I_TH2 to I_TH1.
In an aspect, the threshold current source 306 may be configured without adjustability, i.e., I_THX may be fixed. In an aspect, the threshold current source 306 may be configured to provide adjustability of I_THX, for example, under control of a threshold current control line (not shown) extending from, for example, a control bus (not shown).
It will be appreciated that various exemplary embodiments can provide, among other features, dynamic adjustment of bias current and compensation component values to optimal values for specific sub-ranges of output current, rather than using one set of values over the entire range of output current values, for the purpose of improving output voltage droop and stability performance.
In
The foregoing disclosed devices (such as the devices of
The methods, sequences and/or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
Accordingly, an embodiment of the invention can include a computer readable media embodying a method for implementation. Accordingly, the invention is not limited to illustrated examples and any means for performing the functionality described herein are included in embodiments of the invention.
The foregoing disclosed devices and functionalities may be designed and configured into computer files (e.g., RTL, GDSII. GERBER, etc.) stored on computer readable media. Some or all such files may be provided to fabrication handlers who fabricate devices based on such files. Resulting products include semiconductor wafers that are then cut into semiconductor die and packaged into a semiconductor chip. The chips are then employed in devices described above.
While the foregoing disclosure shows illustrative embodiments of the invention, it should be noted that various changes and modifications could be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the embodiments of the invention described herein need not be performed in any particular order. Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
The present application for patent claims priority to Provisional Application No. 61/720,427 entitled “METHOD AND APPARATUS FOR LOAD ADAPTIVE LDO BIAS AND COMPENSATION” filed Oct. 31, 2012, and assigned to the assignee hereof and hereby expressly incorporated by reference herein.
| Number | Date | Country | |
|---|---|---|---|
| 61720427 | Oct 2012 | US |
