Claims
- 1. A method for writing new data in a computing system having a system memory and a storage device having a plurality of prewrite slots for pre-storage of data and parity information, the method comprising the steps of:providing a scoreboard memory structure in the system memory and operatively coupled to the plurality of prewrite slots to monitor the state of the prewrite slots; in response to a request to store data in the storage device, selecting a prewrite slot from the plurality of prewrite slots based on the contents of the scoreboard memory structure; using the scoreboard memory structure, detecting overlapping prewrites that mandate invalidation of the selected prewrite slot; and invalidating the overlapped prewrite slot in the storage device by conditionally invalidating the corresponding prewrite slot in the scoreboard memory structure without accessing the prewrite slot of the storage device.
- 2. The method of claim 1 further comprising:writing the data and parity information in the selected prewrite slot; and writing the data and parity information to locations in the storage device.
- 3. A method for writing new data in a computing system having a system memory and a storage device, the method comprising the steps of:providing a plurality of prewrite slots in the storage device, each prewrite slot operative to pre-store data and parity information; providing a scoreboard memory structure in the system memory and operatively coupled to the prewrite slots to monitor the state of the prewrite slots; conditionally invalidating an overlapped prewrite slot in the scoreboard memory structure without writing information to the prewrite slot; assigning an identification variable for associating said data and parity information in said prewrite slots across said storage device; and assigning a block variable to each identification variable corresponding to a range of blocks occupied in the storage device.
- 4. A computer program embodied on a propagating signal comprising computer code segments configured to cause a computer having a system memory and a storage device to write new data to the storage device, the program comprising:a first code segment comprising computer code devices configured to cause the computer to create a plurality of prewrite slots in the storage device for pre-storage of data and parity information; a second code segment comprising computer code devices configured to cause the computer to create an instance of a scoreboard memory structure in the system memory that is operatively coupled to the prewrite slots to monitor the state of the prewrite slots; a third code segment comprising computer code devices configured to cause the computer to respond to a request to store data in the storage device, by selecting a prewrite slot from the plurality of prewrite slots based on the contents of the scoreboard memory structure; a fourth code segment comprising computer code devices configured to cause the computer to detect overlapping prewrites that mandate invalidation of the selected prewrite slot; and a fifth code segment comprising computer code devices configured to cause the computer to invalidate the overlapped prewrite slot in the storage device.
- 5. The computer program of claim 4 further comprisinga sixth code segment comprising computer code devices configured to cause the computer to write the data and parity information in the selected prewrite slot; a seventh code segment comprising computer code devices configured to cause the computer to write the data and parity information to locations in the storage device; and an eighth code segment comprising computer code devices configured to cause the computer to conditionally invalidate the corresponding prewrite slot in the scoreboard memory structure without accessing the prewrite slot of the storage device once data is written to the storage location.
CROSS REFERENCE TO RELATED APPLICATION
This is a division of application Ser. No. 08/767,720, filed on Dec. 17, 1996 and now issued as U.S. Pat. No. 5,859,965 which is hereby incorporated by reference in its entirety.
This patent application is related to the following co-pending, commonly-assigned U.S. Patent Application, the disclosure of which is expressly and specifically incorporated herein by reference in its entirety: U.S. Pat. No. 5,734,814 entitled “HOST-BASED RAID-5 AND NV-RAM INTEGRATION”, by Robert S. Gittins and John R. Corbin, filed Apr. 15, 1996, Ser. No. 08/631,934.
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