Claims
- 1. A processor responsive to a clock cycle, comprising:
a base-unit for providing an output signal in response to an input signal; a mirror-unit for providing an output signal in response to the input signal, the mirror-unit being a duplicate instance of the base-unit; a first staging register disposed at the input to the mirror-unit for delaying the input signal thereto by at least one clock cycle; a second staging register disposed at the output of the mirror-unit for delaying the output signal therefrom by at least one clock cycle; and a non-duplicated-unit in signal communication with the base and mirror units, the non-duplicated-unit having a comparator for comparing the output signals of the base and mirror units.
- 2. The processor of claim 1, wherein the non-duplicated-unit comprises a recovery-unit, and further comprising:
third and fourth staging registers serially disposed between the base-unit and the comparator for delaying the output signal of the base-unit by at least two clock cycles.
- 3. The processor of claim 2, wherein:
the base-unit, the mirror-unit and the non-duplicated-unit define a first processor core having asymmetrical mirroring; wherein the base-unit and non-duplicated unit in the first processor core are floorplanned closer together than the base-unit and non-duplicated unit in a second processor core, the second processor core having the base-unit, the mirror-unit, the non-duplicated-unit and symmetrical mirroring.
- 4. The processor of claim 1, wherein:
the base and mirror units comprise at least one of instruction-units, execution-units, or any combination thereof.
- 5. The processor of claim 1, wherein the base and mirror units comprise instruction-units, and further comprising:
an execution-base-unit and an execution-mirror-unit; wherein the base-units are disposed closer to each other than to their respective mirror-units.
- 6. The processor of claim 5, wherein:
each input of each mirror unit has a first staging register, and each output of each mirror unit has a second staging register.
- 7. A method of cycling a processor, comprising:
running a mirror-unit one cycle later than its associated base-unit; perceiving at a non-duplicated-unit that the mirror-unit is running two cycles behind its associated base-unit; and realigning the mirror and base unit signals at the non-duplicated-unit for comparison.
- 8. The method of claim 7, further comprising:
detecting a miscompare on the signals received from the base and mirror units at least two cycles later than the occurrence of the miscompare event.
- 9. The method of claim 7, further comprising:
sourcing a low priority function signal from the mirror unit.
- 10. A processor, comprising:
a base functional core comprising a base-unit of a duplicated unit and a non-duplicated unit, the base-unit being in signal communication with the non-duplicated unit; a non-functional instance area comprising a mirror-unit of the duplicated unit, the non-functional instance area being in signal communication with the base functional core; and a register bank disposed between the base functional core and the mirror-unit; wherein signals received at the mirror-unit are delayed at the register bank by at least one clock cycle with respect to signals received at the base-unit.
- 11. The processor of claim 10, wherein:
the non-duplicated unit comprises a comparator, and a second register bank disposed between the comparator and the base-unit; wherein signals received at the comparator from the base-unit are delayed at the second register bank by at least one clock cycle, thereby aligning the base-unit signals received at the comparator with the delayed mirror-unit signals received at the comparator.
- 12. The processor of claim 11, wherein:
the second register bank is in an encoded form, thereby reducing processor real estate usage.
RELATED APPLICATIONS
[0001] The present application is related to the co-pending United States patent application “Method and Apparatus for Controlling Clocks in a Processor with Mirrored Units” (DISCLOSURE NUMBER: POU820030058, DOCKET NUMBER: POU920030095US1) filed by Timothy McNamara, Michael Billeci, David Webber and Ching L. Tong.
[0002] The co-pending application and the present application are owned by one and the same assignee, International Business Machines Corporation of Armonk, N.Y. The descriptions set forth in the co-pending application are hereby incorporated into the present application by this reference.
[0003] Trademarks: IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. S/390, Z900 and z990 and other product names may be registered trademarks or product names of International Business Machines Corporation or other companies.