Claims
- 1. A method for mismatch shaping, comprising the steps of:
(a) receiving a digital input code; (b) producing a range signal based on the digital input code, the range signal specifying which one of a plurality of ranges the digital input code is within; (c) producing a density code, the density code specifying a level within the range expressed by the range signal; and (d) combining the range signal and the density code to thereby produce a plurality of sub-codes, a sum of the plurality of sub-codes equaling the digital input code.
- 2. The method of claim 1, wherein step (c) comprises selecting one of a plurality of orders for the density code using a shuffling algorithm, wherein each of the orders specify an order of bits in the density code.
- 3. The method of claim 2, wherein the shuffling algorithm comprises a dynamic element mismatch shaping algorithm, and wherein step (c) comprises selecting the one of the plurality of orders for the density code using the dynamic element mismatch shaping algorithm.
- 4. The method of claim 2, wherein step (c) comprises selecting the one of the plurality of orders for the density code based on at least one of:
(c.1) one or more sub-code orders that were previously selected, and (c.2) a pseudo random code.
- 5. The method of claim 2, further comprising:
(e) shuffling each of the plurality of sub-codes to produce a plurality of shuffled sub-codes.
- 6. The method of claim 1, further comprising the step of:
(f) providing each of the plurality of shuffled sub-codes to a respective multi-element sub-digital-to-analog converter (sub-DAC).
- 7. The method of claim 1, wherein step (b) comprises producing the range signal based on a portion of the digital input code.
- 8. The method of claim 1, wherein the digital input code comprises a multi-bit binary word, and wherein step (b) comprises producing the range signal based on at least the two most significant bits of the binary word.
- 9. The method of claim 1, wherein step (c) comprises producing the density code based on a portion of the digital input code.
- 10. The method of claim 1, wherein the digital input code comprises a multi-bit binary word, and wherein step (c) comprises producing the density code based on at least the two least significant bits of the binary word.
- 11. The method of claim 1, wherein step (c) comprises:
(c.1) producing a modulo signal specifying a difference between the digital input code and a lower end of the range specified by the range signal; and (c.2) producing the density code based on the modulo signal.
- 12. The method of claim 1,
wherein the density code is comprised of K bits, where K>1, and wherein step (d) comprises separately adding each of the K bits to the range signal to thereby produce K separate sub-codes, the K separate sub-codes being the plurality of sub-codes.
- 13. The method of claim 10, further comprising the steps of:
(e) shuffling each of the K sub-codes to produce K shuffled sub-codes; and (f) providing each of the K shuffled sub-codes to a respective multi-element sub-digital-to-analog converter (sub-DAC).
- 14. The method of claim 1, further comprising repeating steps (a) through (d) a plurality of times.
- 15. The method of claim 14, wherein bits of the shuffled density code can have one of a plurality of different orders for a specific digital input code, and
wherein step (c) further comprises selecting one of the different orders such that, on average, each one of the different orders is selected substantially the same number of times.
- 16. A method for mismatch shaping, comprising the steps of:
receiving a digital input code having a first value V1; producing a second digital value V2, wherein V2 equals a greatest integer less than V1÷K, where K>2; producing a third digital value V3, wherein V3 equals V1 modulo K; producing a shuffled density code based on the third digital value V3, wherein the shuffled density code includes K bits each of which has a value of 0 or 1, and wherein an order of the K bits with respect to one another is based on a shuffling algorithm; separately adding V2 to each of the K bits to produce K separate further digital outputs V41 . . . V4K, wherein a sum of the K separate further digital outputs equals the first value V1 [i.e., 3V1[i.e.,∑i=1kV4i=V1].
- 17. The method of claim 16, wherein the shuffling algorithm comprises a dynamic element mismatch shaping algorithm, and wherein the step of producing a shuffled density code is performed using the dynamic element mismatch shaping algorithm.
- 18. The method of claim 16, further comprising the steps of:
providing each the K separate further digital outputs V41 . . . V4K to one of K separate shufflers; and separately shuffling each of the digital outputs V41 . . . V4K using one of the K shufflers to produce a respective shuffled sub-code, thereby producing K shuffled sub-codes for each digital input code.
- 19. The method of claim 18, further comprising the steps of:
providing each of the K shuffled sub-codes to a separate one of K multi-bit sub-digital-to-analog converters (sub-DACs); and converting each of the K shuffled sub-codes to analog signals using a respective one of the K muti-bit sub-DACs, thereby producing a plurality of analog signals, wherein a sum of the plurality of analog signals is representative of the first value V1.
- 20. The method of claim 18, further comprising the steps of:
separately shuffling each of the digital outputs V41 . . . V4K to produce a respective shuffled sub-code, thereby producing K shuffled sub-codes for each digital input code; and converting each of the K shuffled sub-codes to analog signals using a respective one of the K muti-bit sub-DACs, thereby producing a plurality of analog signals, wherein a sum of the plurality of analog signals is representative of the first value V1.
- 21. An apparatus for mismatch shaping, comprising:
a range selector to produce a range signal based on the digital input code, the range signal specifying which one of a plurality of ranges the digital input code is within; a density generator to produce a density code, the density code specifying a level within the range expressed by the range signal; and a combiner to combine the range signal and the density code to thereby produce a plurality of sub-codes, a sum of the plurality of sub-codes equaling the digital input code.
- 22. The apparatus of claim 21, wherein the density generator selects one of a plurality of orders for the density code using a shuffling algorithm, wherein each of the orders specify an order of bits in the density code.
- 23. The apparatus of claim 22, wherein the density generator includes a dynamic element mismatch shaping circuit to select one of a plurality of orders for the density code, wherein each of the orders specify an order of bits in the density code.
- 24. The apparatus of claim 22, wherein the density generator selects one of a plurality of orders for the density code based on at least one of:
(a) one or more orders that were previously selected, and (b) a pseudo random code.
- 25. The apparatus of claim 24, further comprising:
a shuffler for each of the plurality of sub-codes, wherein each shuffler shuffles a respective one of the plurality of sub-codes, to thereby produce a plurality of shuffled sub-codes.
- 26. The apparatus of claim 21, further comprising:
a sub-digital-to-analog converter (sub-DAC) for each of the plurality of shuffled sub-codes, wherein each of the sub-DACs receives a respective one of the shuffled sub-codes and produces analog signals therefrom, wherein a sum of the analog signals from all of the sub-DACs is representative of the received digital input signal.
- 27. The apparatus of claim 21, wherein the range selector produces the range signal based on a portion of the digital input code.
- 28. The apparatus of claim 21, wherein the digital input code comprises a multi-bit binary word, and wherein the range selector produces the range signal based on at least the two most significant bits of the binary word.
- 29. The apparatus of claim 21, wherein the density generator produces the density code based on a portion of the digital input code.
- 30. The apparatus of claim 21, wherein the digital input code comprises a multi-bit binary word, and wherein the range selector produces the density code based on at least the two least significant bits of the binary word.
- 31. The apparatus of claim 21, further comprising a means for producing a modulo signal specifying a difference between the digital input code and a lower end of the range specified by the range signal, wherein the density generator produces the density codes based on the modulo signal.
- 32. The apparatus of claim 21, wherein the density code is comprised of K bits, where K>1, and wherein the combiner separately adds each of the K bits to the range signal to thereby produce K separate sub-codes, the K separate sub-codes being the plurality of sub-codes.
- 33. The apparatus of claim 29, further comprising:
K shufflers, each shuffling one of the K sub-codes, to thereby produce K shuffled sub-codes; and K multi-element sub-digital-to-analog converter (sub-DAC), wherein each of the K multi-element sub-DACs receives a respective one of the K shuffled sub-codes and converts the one of the K shuffled sub-codes to analog signals, wherein a sum the analog signals produced by all of the K multi-element sub-DACs is representative of the digital input code.
- 34. The apparatus of claim 33, further comprising a means for combining the analog signals produced by all of the K multi-element sub-DACs to produce a combined analog signal representative of the digital input code.
- 35. The apparatus of claim 24, wherein bits of the shuffled density code can have one of a plurality of different orders for a specific digital input code, and
wherein the density generator selects one of the different orders such that, on average, each one of the different orders is selected substantially the same number of times.
- 36. An apparatus for mismatch shaping, comprising:
means for receiving a digital input code having a first value V1; means for producing a second digital value V2, wherein V2 equals a greatest integer less than V1÷K, where K>2; means for producing a third digital value V3, wherein V3 equals V1 modulo K; means for producing a shuffled density code based on the third digital value V3, wherein the shuffled density code includes K bits each of which has a value of 0 or 1, and wherein an order of the K bits with respect to one another is based on a shuffling algorithm; and means for separately adding V2 to each of the K bits to produce K separate further digital outputs V41 . . . V4K, wherein a sum of the K separate further digital outputs equals the first value V1 [i.e., 4value V1[i.e.,∑i=1k V4i=V1].
- 37. The apparatus of claim 36, wherein the means for producing a shuffled density code includes a dynamic element mismatch shaping circuit.
- 38. The apparatus 26, further comprising:
K shufflers, each to shuffle a respective one of the further digital outputs V41 . . . V4K, to thereby produce K shuffled sub-codes for each digital input code.
- 39. The apparatus of claim 38, further comprising:
K multi-bit sub-digital-to-analog converters (sub-DACs), each to convert one of the K shuffled sub-codes to analog signals, wherein a sum of the analog signals from all of the K multi-bit sub-DACs is representative of the first value V1.
- 40. The apparatus of claim 39, further comprising a means for combining the analog signals produced by all of the K multi-element sub-DACs to produce a combined analog signal representative of the first value V1.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The application claims priority to U.S. Provisional Patent Application No. 60/231,991, entitled “A Mismatch Shaping Method for Oversampled Data Converters,” filed Sep. 11,2000, and U.S. Provisional Patent Application No. 60/232,155, entitled “A Mismatched Shaping Method for Oversampled Data Converters for Use in an Analog Front End in a DOCSIS Compatible Cable Modem,” filed Sep. 11, 2000, both of which are assigned to the assignee of the present invention, and both of which are incorporated herein by reference in their entirety.
[0002] This application is related to commonly assigned U.S. patent application Ser. No. ______ (Attorney Docket No. 1875.0860001), also entitled “Method and Apparatus for Mismatch Shaping of an Oversampled Converter,” filed the same day as the present application, and incorporated herein by reference.
Provisional Applications (2)
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Number |
Date |
Country |
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60231991 |
Sep 2000 |
US |
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60232155 |
Sep 2000 |
US |