Patent Application
20140184908
The present invention relates to multimedia synchronization. More particularly, it relates to the synchronization of video and audio multimedia streams.
Audio & video stream synchronization is typically accomplished by comparing the timestamps of an audio or video stream to a master clock and playing back the sample when the timestamps of the stream match the timing of the master clock. Typically, a master clock is considered to be a clock that is accessible for most streams that are to be synchronized together.
Sometimes when a stream is generated, the timestamps associated with the stream are in reference to a clock that is not available to the stream. It was then likely that this stream would be out of synchronization with the master clock if the timestamps associated with this stream do not correlate with the master clock. To solve this problem, the timing of the master clock would be adjusted to as to synchronize itself with the stream that lacked access to the unavailable reference clock. This solution however would not work well if two or more streams lacked access to their respective reference clocks because an adjustment to the master clock for one stream would not solve the timing problems associated with the second stream.
According to an implementation, an apparatus and method are described for providing synchronization for different multimedia streams and metadata. Each multimedia stream is associated with a child clock which can be implemented in software, hardware, or a combination thereof. Once the child clocks are spawned, one of the child clocks is designated as a master clock which becomes the controlling clock for the synchronization operation.
These and other aspects, features and advantages of the present principles will become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.
The present principles may be better understood in accordance with the following exemplary figures, in which:
The present principles are directed to synchronizing multimedia streams. The present description illustrates the present principles. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the present principles.
Moreover, all statements herein reciting principles, aspects, and embodiments of the present principles, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.
Thus, for example, it will be appreciated by those skilled in the art that the block diagrams presented herein represent illustrative circuitry embodying the present principles. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudocode, and the like represent various processes which may be substantially represented in computer readable media and so executed by a computer or processor, whether or not such computer or processor is explicitly shown. In addition, it is expected that the computer code used to implemented the described principles can exist in a non-transitory state form, as well.
The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term “processor” or “controller” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (“DSP”) hardware, read-only memory (“ROM”) for storing software, random access memory (“RAM”), non-volatile storage, and the like.
Other hardware, conventional and/or custom, may also be included. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.
In the claims hereof, any element expressed as a means for performing a specified function is intended to encompass any way of performing that function including, for example, a) a combination of circuit elements that performs that function or b) software in any form, including, therefore, firmware, microcode or the like, combined with appropriate circuitry for executing that software to perform the function. The present principles as defined by such claims reside in the fact that the functionalities provided by the various recited means are combined and brought together in the manner which the claims call for. It is thus regarded that any means that can provide those functionalities are equivalent to those shown herein.
As mentioned above, stream synchronization becomes a challenging task as the number and type of streams to be synchronized grow and become more varied. According to an embodiment of the presented principles, multimedia synchronization is achieved through the implementation of a hierarchical clock based system.
Within the execution of synchronization scheme 10, other streams will only be able read the central clock to compare the timestamps within such streams to the central clock 12. That is, such other streams will not be able to affect the timing of the central clock 12 when an adjustment is made to the central clock 12 to accommodate a stream when such as stream lacks access to reference clock.
Other problems with system 10 include that is unlikely that the single central clock 12 can be used to have audio and video streams of unequal length rollover in a synchronized fashion. Also, system 10 is unlikely able to synchronize streams at a random point in a media processing chain.
Any type of child clock 26, 28, including a software clock can be nominated as the master clock. By using software based child clocks 26, 28 for each stream, synchronization system 25 becomes more flexible that the system shown in
The principles described herein can also be used to synchronize audio and video with other types of metadata. For example, film grain metadata for an Advanced Video Coding (AVC) compressed video stream can be stored/transmitted using an out-of-band mechanism like log files. The addition of a film grain effect into a video frame typically occurs when a compressed video frame is decoded but before it is temporally re-aligned for display. When the grain information is read from a file, each grain sample needs to be correctly synchronized with the video frame to which it needs to be applied. Under the new scheme, a film grain synchronization operation can be accomplished by creating two child clocks 26, 28, one for the video stream and one for the film grain metadata stream, whereby both the metadata for the film grain operation and the video stream can then be associated with parent clock 20.
Referring back to system 25 in
In a related example, metadata related to offering a user a two screen experience can be used for controlling the output to a second screen device such as a tablet or computer where commands, video, audio, or a combination thereof can be outputted to a second screen device. The present principles would assign a child clock 26, 28 to the metadata that is for the second screen while another child clock 26, 28 is assigned to video stream 18 for output on a primary device such as a television. The metadata for the second screen can be controlled by the child clock 26, 28 so that is synchronized with both video stream 18 and parent clock 20. Moreover, a third child clock 26, 28 could be used to synchronize audio stream 20 with video stream 18 and the second screen metadata in accordance with the described principles.
In other implementations of the present principles, more than one parent clock 20 can exist simultaneously, thereby making it possible to have multiple independent synchronization systems in the same computer application and/or hardware. This is further illustrated by the previous examples where the synchronization of metadata and video for grain insertion happens independently and in addition to the audio and video synchronization performed at a rendering stage.
Due to the hierarchical nature of the present system, parent clock 20 can maintain a rollover state of the system as a whole. This allows parent clock 20 to control the child clocks 26, 28 to rollover in a synchronized fashion when needed. Most streaming players buffer or prefetch a stream to smooth out jitter in the inter arrival time of network packets. When content with unequal length audio and video tracks is streamed in a continuous loop, the two streams will rollover at different times at the video player. This skew can be mitigated by controlling the rollover and prefetch states of the system. To resolve this problem, as shown in
These and other features and advantages of the present principles may be readily ascertained by one of ordinary skill in the pertinent art based on the teachings herein. It is to be understood that the teachings of the present principles may be implemented in various forms of hardware, software, firmware, special purpose processors, or combinations thereof.
Most preferably, the teachings of the present principles are implemented as a combination of hardware and software. Moreover, the software may be implemented as an application program tangibly embodied on a program storage unit. The application program may be uploaded to, and executed by, a machine comprising any suitable architecture. Preferably, the machine is implemented on a computer platform having hardware such as one or more central processing units (“CPU”), a random access memory (“RAM”), and input/output (“I/O”) interfaces. The computer platform may also include an operating system and microinstruction code. The various processes and functions described herein may be either part of the microinstruction code or part of the application program, or any combination thereof, which may be executed by a CPU. In addition, various other peripheral units may be connected to the computer platform such as an additional data storage unit and a printing unit.
It is to be further understood that, because some of the constituent system components and methods depicted in the accompanying drawings are preferably implemented in software, the actual connections between the system components or the process function blocks may differ depending upon the manner in which the present principles are programmed. Given the teachings herein, one of ordinary skill in the pertinent art will be able to contemplate these and similar implementations or configurations of the present principles.
Although the illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the present principles is not limited to those precise embodiments, and that various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present principles. All such changes and modifications are intended to be included within the scope of the present principles as set forth in the appended claims.
