Claims
- 1. A method of ordering interconnect transactions in a computer system, comprising the steps of:
(a) receiving an interconnect transaction from an interconnect interface, the interconnect interface operating according to an interconnect protocol; (b) identifying a transaction type of the interconnect transaction; (c) enqueuing the interconnect transaction as a queued transaction on a transaction ordering queue (TOQ), imposing a stricter ordering on the interconnect transaction than an interconnect-protocol-imposed ordering; and (d) dequeuing the queued transaction from the TOQ as a dequeued transaction.
- 2. The method of claim 1, further comprising the steps of:
if the interconnect transaction is of a second transaction type and no transactions of a first transaction type are in the TOQ, bypassing step (c).
- 3. The method of claim 1, wherein the interconnect interface operates according to the PCI-X extension of the PCI protocol.
- 4. The method of claim 3, wherein the second transaction type is a relaxed ordering type transaction type and the first transaction type is a non-relaxed ordering transaction type.
- 5. The method of claim 1, wherein step (d) is performed once per clock cycle, if any transactions are in the TOQ.
- 6. The method of claim 1, step (d) comprising the steps of:
determining whether any transaction of the first transaction type is awaiting execution; if no transactions of the first transaction type are awaiting execution, dequeuing the queued transaction from the TOQ as a dequeued transaction; and scheduling the dequeued transaction for execution.
- 7. The method of claim 6, step (d) further comprising the steps of:
determining whether the queued transaction is of the second transaction type; if the queued transaction is of the second transaction type, then dequeuing the queued transaction as a dequeued transaction; and scheduling the dequeued transaction for execution.
- 8. A method of ordering interconnect transactions in a computer system, comprising the steps of:
detecting an interconnect transaction of a predetermined type according to an interconnect protocol; and ordering the interconnect transaction using a stricter ordering than imposed by the interconnect protocol.
- 9. The method of claim 8, wherein the predetermined type is a relaxed ordering type.
- 10. The method of claim 9, wherein the interconnect protocol is the PCI-X extension to the PCI protocol, and
wherein the relaxed ordering type is indicated by a relaxed ordering attribute in an attribute phase of the interconnect transaction.
- 11. The method of claim 8, the step of ordering the interconnect transaction comprising the step of:
placing the interconnect transaction in a transaction ordering queue.
- 12. A system for ordering interconnect transactions in a computer system, comprising:
an interconnect interface, coupled to an interconnect operating according to an interconnect protocol, adapted to receive interconnect transactions; and a transaction ordering queue (TOQ), coupled to the interconnect interface, adapted to queue interconnect transactions received by the interconnect interface as queued transactions of a first transaction type and a second transaction type, imposing a stricter ordering on the interconnect transactions than an interconnect-protocol-imposed ordering, further adapted to dequeue queued transactions as dequeued transactions.
- 13. The system of claim 12,
wherein the interconnect protocol allows interconnect transactions of the second transaction type to pass interconnect transactions of the first transaction type and interconnect transactions of the second transaction type, and wherein an interconnect transactions of the second transaction type enqueued in the TOQ can not pass an interconnect transactions of the first transaction type previously enqueued in the TOQ.
- 14. The system of claim 12, the TOQ comprising:
circuitry to queue interconnect transactions in a first-in-first-out (FIFO) queue; and circuitry to dequeue a queued transaction from the FIFO queue.
- 15. The system of claim 14, the circuitry to queue interconnect transactions in a FIFO queue comprising:
circuitry to bypass queuing an interconnect transaction of the second transaction type in the FIFO queue if no interconnect transactions of the first transaction type are in the FIFO queue.
- 16. The system of claim 14, the circuitry for dequeuing transaction from the FIFO queue comprising:
a first circuitry to determine whether any interconnect transactions of the first transaction type or the second transaction type are awaiting execution; and a second circuitry to dequeue a transaction from the FIFO queue if no interconnect transactions of the first transaction type or the second transaction type are awaiting execution.
- 17. The system of claim 16, further comprising:
a third circuitry to determine whether a first transaction of the FIFO queue is an interconnect transaction of the second type; and a fourth circuitry to dequeue the first transaction from the FIFO queue if the first transaction is of the second type.
- 18. The system of claim 12,
wherein the interconnect protocol is the PCI-X extension to the PCI protocol, wherein interconnect transactions of the second transaction type have the Relaxed Ordering attribute set in an attribute phase of the interconnect transactions, and wherein interconnect transactions of the first transaction type have the Relaxed Ordering attribute unset in the attribute phase of the interconnect transactions.
- 19. The system of claim 12, wherein interconnect transactions of the second transaction type are not enqueued in the TOQ if no interconnect transactions of the first transaction type are in the TOQ.
- 20. The system of claim 12, wherein the interconnect interface and the TOQ are implemented in an application-specific integrated circuit (ASIC).
- 21. The system of claim wherein the interconnect interface and the TOQ are implemented in a PCI-X host bridge.
- 22. The system of claim 12, further comprising:
a plurality of buffers, the plurality of buffers storing the interconnect transactions, wherein the TOQ stores information corresponding to the interconnect transactions sufficient to order the interconnect transactions.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The following related patent applications are hereby incorporated by reference as if set forth in their entirety:
[0002] U.S. patent application Ser. No. 09/749,111, entitled “Relaxed Read Completion Ordering in a System Using a Transaction Order Queue,” filed Dec. 26, 2000;
[0003] U.S. patent application Ser. No. 09/779,424, entitled “Enhancement to Transaction Order Queue,” filed Feb. 8, 2001;
[0004] U.S. patent application Ser. No. 10/038,844, entitled “System to Optimally Order Cycles Originating from a Single Physical Link,” filed Dec. 31, 2001;
[0005] U.S. patent application Ser. No. 10/039,130, entitled “Inter-Queue Ordering Mechanism,” filed Dec. 31, 2001; and
[0006] U.S. Patent Application Serial No. 10/______, entitled “Method and Apparatus for Ordering Interconnect Transactions in a Computer System,” filed concurrently, bearing Attorney Docket No. H052617.1296US0.