Patent Application
20210255783
The present invention is related to memory control, and more particularly, to a method and apparatus for performing data storage management to enhance data reliability, for example, with aid of repeated write command detection.
Developments in memory technology have led to the wide applications of portable or non-portable memory devices (e.g. a memory card conforming to the SD/MMC, CF, MS or XD specification, a solid-state drive (SSD), and an embedded memory device conforming to the UFS or eMMC specification). Thus, improving access control of memories in these memory devices remains an issue to be solved in the art.
NAND flash memories may typically comprise single level cell (SLC) and multiple level cell (MLC) flash memories. In an SLC flash memory, each transistor used as a memory cell may have any of two electrical charge values, respectively representing the logic values 0 and 1. In addition, the storage ability of each transistor used as a memory cell in an MLC flash memory may be fully utilized, where the transistor is driven by a voltage higher than that in the SLC flash memory, to record information of at least two bits (e.g. 00, 01, 11, or 10) in a transistor through different voltage levels. In theory, the recording density of the MLC flash memory may reach at least twice the recording density of the SLC flash memory, and is therefore preferred by manufacturers of NAND flash memories.
Compared with the SLC flash memory, the lower cost and larger capacity of the MLC flash memory means it is more likely to be applied in memory devices. The MLC flash memory does have instability issues, however. To ensure that access control of the flash memory in the memory device meets related specifications, a controller of the flash memory is usually configured to have management mechanisms to properly manage the access of data.
Related art memory devices with the above management mechanisms still have some disadvantages. For example, a host system such as a multifunctional mobile phone, a tablet, an all-in-one (AIO) computer, a laptop computer, etc. may store various kinds of user data of a user into a memory device therein. When it is needed that the memory device conforms to a certain specification, the memory device may merely perform some basic operations such as reading, writing, etc. as requested by the host system, and there may be no additional command for inter-device communications. As a result, the memory device may store the user data of the user in a data region of the memory device in a cost-effective manner by default, without any special treatment, since no additional command for inter-device communications is available. Thus, a novel method and associated architecture are needed for improving performance of memory devices without introducing any side effect or in a way that is less likely to introduce a side effect.
It is therefore an objective of the present invention to provide a method for performing data storage management to enhance data reliability, for example, with aid of repeated write command detection, and to provide associated apparatus such as a memory device, a controller thereof, an electronic device comprising the memory device, etc., in order to solve the above-mentioned problems.
At least one embodiment of the present invention provides a method for performing data storage management to enhance data reliability, where the method may be applied to a memory device. The memory device may comprise a non-volatile (NV) memory, the NV memory may comprise at least one NV memory element (e.g. one or more NV memory elements), and the aforementioned at least one NV memory element may comprise a plurality of blocks. The method may comprise: receiving a write command from a host system, wherein the write command indicates that writing a set of data into the NV memory is required; determining whether a repeated writing condition is satisfied, wherein the repeated writing condition comprises the write command being a repeated write command of a previous write command and corresponding to a same address and a same length as that of the previous write command; and in response to the repeated writing condition being satisfied, storing the set of data into at least one first type block of a first type of blocks within the NV memory, for performing data storage enhancement processing, wherein a first bit count of one or more bits stored in a memory cell of any of the first type of blocks is less than a second bit count of multiple bits stored in a memory cell of any of a second type of blocks within the NV memory.
In addition to the above method, the present invention also provides a memory device, and the memory device comprises a NV memory and a controller. The NV memory is arranged to store information, wherein the NV memory may comprise at least one NV memory element (e.g. one or more NV memory elements), and the aforementioned at least one NV memory element may comprise a plurality of blocks. The controller is coupled to the NV memory, and the controller is arranged to control operations of the memory device. In addition, the controller comprises a processing circuit that is arranged to control the controller according to a plurality of host commands from a host system, to allow the host system to access the NV memory through the controller. For example, the controller receives a write command from the host system, wherein the write command indicates that writing a set of data into the NV memory is required; the controller determines whether a repeated writing condition is satisfied, wherein the repeated writing condition comprises the write command being a repeated write command of a previous write command and corresponding to a same address and a same length as that of the previous write command; and in response to the repeated writing condition being satisfied, the controller stores the set of data into at least one first type block of a first type of blocks within the NV memory, for performing data storage enhancement processing, wherein a first bit count of one or more bits stored in a memory cell of any of the first type of blocks is less than a second bit count of multiple bits stored in a memory cell of any of a second type of blocks within the NV memory.
According to some embodiments, an associated electronic device is also provided. The electronic device may comprise the above memory device, and may further comprise the host system. In addition, the host system may comprise a host device, and the host device may be coupled to the memory device. The host device may comprise: at least one processor, arranged for controlling operations of the host device; and a power supply circuit, coupled to the at least one processor, arranged for providing power to the at least one processor and the memory device. In addition, the memory device may provide the host device with storage space.
In addition to the above method, the present invention also provides a controller of a memory device, where the memory device comprises the controller and a NV memory. The NV memory may comprise at least one NV memory element (e.g. one or more NV memory elements), and the aforementioned at least one NV memory element may comprise a plurality of blocks. In addition, the controller comprises a processing circuit that is arranged to control the controller according to a plurality of host commands from a host system, to allow the host system to access the NV memory through the controller. For example, the controller receives a write command from the host system, wherein the write command indicates that writing a set of data into the NV memory is required; the controller determines whether a repeated writing condition is satisfied, wherein the repeated writing condition comprises the write command being a repeated write command of a previous write command and corresponding to a same address and a same length as that of the previous write command; and in response to the repeated writing condition being satisfied, the controller stores the set of data into at least one first type block of a first type of blocks within the NV memory, for performing data storage enhancement processing, wherein a first bit count of one or more bits stored in a memory cell of any of the first type of blocks is less than a second bit count of multiple bits stored in a memory cell of any of a second type of blocks within the NV memory.
The present invention method and associated apparatus can guarantee that the memory device can operate properly in various situations. With aid of the present invention method and associated apparatus, the memory device will not suffer from the existing problems of the related art. In addition, implementing the embodiments of the present invention will not greatly increase additional costs. Thus, problems existing in the related art can be solved without greatly increasing the overall cost. In comparison with the related art, the present invention can achieve optimal performance of memory devices without introducing side effects or in a way that is less likely to introduce side effects.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
According to this embodiment, the memory device 100 may comprise a controller such as a memory controller 110, and may further comprise a non-volatile (NV) memory 120, where the controller is arranged to access the NV memory 120, and the NV memory 120 is arranged to store information. The NV memory 120 may comprise at least one NV memory element (e.g. one or more NV memory elements), such as a plurality of NV memory elements 122-1, 122-2, . . . , and 122-N, where “N” may represent a positive integer that is greater than one. For example, the NV memory 120 may be a flash memory, and the plurality of NV memory elements 122-1, 122-2, . . . , and 122-N may be a plurality of flash memory chips (which may be referred to as flash chips) or a plurality of flash memory dies (which may be referred to as flash dies), respectively, but the present invention is not limited thereto. As shown in
In this embodiment, the host system 20 (more particularly, the host device 50, with aid of the bridge device 60) may transmit a plurality of host commands and corresponding logical addresses to the memory controller 110, to access the NV memory 120 within the memory device 100, indirectly. The memory controller 110 receives the plurality of host commands and the logical addresses, and translates the plurality of host commands into memory operating commands (which may be referred to as operating commands, for brevity), respectively, and further controls the NV memory 120 with the operating commands to perform reading or writing/programing upon the memory units (e.g. data pages) of specific physical addresses within the NV memory 120, where the physical addresses may be associated with the logical addresses. For example, the memory controller 110 may generate or update at least one logical-to-physical address mapping table to manage the relationship between the physical addresses and the logical addresses. The NV memory 120 may store a management table 120MT, for the memory controller 110 to control the memory device to manage blocks storing user data that has been processed with certain treatment. When there is a need, the memory controller 110 may load the management table 120MT into the buffer memory 116 or other memories. The management table 120MT may be positioned in a predetermined region within the NV memory element 122-1, such as a system region, but the present invention is not limited thereto. In some embodiments, the management table 120MT may be positioned in any of the NV memory elements 122-1, 122-2, . . . , and 122-N.
In addition, the aforementioned at least one NV memory element (e.g. the one or more NV memory elements such as {122-1, 122-2, . . . , 122-N}) may comprise a plurality of blocks, where the minimum unit that the memory controller 110 may perform operations of erasing data on the NV memory 120 may be a block, and the minimum unit that the memory controller 110 may perform operations of writing data on the NV memory 120 may be a page, but the present invention is not limited thereto. For example, any NV memory element 122-n within the NV memory elements 122-1, 122-2, . . . , and 122-N (where “n” may represent any integer in the interval [1,N]) may comprise a group of blocks, and a block within the group of blocks may comprise and record specific number of pages, where the memory controller 110 may access a certain page of a certain block within the group of blocks according to a block address and a page address. For another example, the NV memory element 122-n may comprise multiple planes, and any plane of the multiple planes may comprise a set of blocks such as the group of blocks, where the memory controller 110 may access a certain page of a certain block of a certain plane within the multiple planes according to a plane number, a block address and a page address.
Based on the architecture shown in
In Step S10, the memory controller 110 may receive a command from the host system 20, such as one of the plurality of host commands.
In Step S12, the memory controller 110 may determine whether the command is a write command. If Yes, the memory controller 110 may execute Step S14; If No, the memory controller 110 may execute Step S16. For example, the command may represent the write command (e.g. the memory controller 110 may receive the write command from the host system 20 in Step S10), and the write command may indicate that writing a set of data into the NV memory 120 is required, but the present invention is not limited thereto. For another example, the command may represent a read command, and the read command may indicate that reading one or more sets of data from the NV memory 120 is required.
In Step S14, the memory controller 110 may determine whether a repeated writing condition is satisfied, where the repeated writing condition may comprise the write command being a repeated write command of a previous write command and corresponding to a same address and a same length as that of the previous write command. If Yes, the memory controller 110 may execute Step S20; If No, the memory controller 110 may execute Step S30. According to this embodiment, in a situation where the command mentioned in Step S10 represents the write command, the memory controller 110 may determine whether this write command is the next write command of the previous write command, and more particularly, may determine whether this write command indicates that writing data of the same length at the same address (e.g. the same logical address) is required. For example, when this write command is the next write command of the previous write command and indicates that writing data of the same length at the same address (e.g. the same logical address) is required, the memory controller 110 may determine that the repeated writing condition is satisfied, and therefore Step S20 is entered; otherwise, the memory controller 110 may determine that the repeated writing condition is not satisfied, and therefore Step S30 is entered; but the present invention is not limited thereto.
In Step S16, when the command is not the write command (e.g. the command may represent the read command), the memory controller 110 may perform other processing, rather than writing.
In Step S20, in response to the repeated writing condition being satisfied, the memory controller 110 may execute a data storage enhancement procedure, to perform data storage enhancement processing using at least one first type block of a first type of blocks within the NV memory 120. More particularly, a first bit count BITCNT(1) of one or more bits (e.g. BITCNT(1) bits) stored in a memory cell of any of the first type of blocks is less than a second bit count BITCNT(2) of multiple bits (e.g. BITCNT(2) bits) stored in a memory cell of any of a second type of blocks within the NV memory 120, and the reliability of the first type of blocks is greater than that of the second type of blocks. For example, the first type of blocks may comprise a group of single level cell (SLC) blocks, and the second type of blocks may comprise a group of triple level cell (TLC) blocks, where the first bit count BITCNT(1) and the second bit count BITCNT(2) may be equal to one and three, respectively, but the present invention is not limited thereto.
In Step S30, in response to the repeated writing condition being not satisfied, the memory controller 110 may store data (e.g. the set of data) into at least one second type block of the second type of blocks within the NV memory 120.
Based on the working flow shown in
For better comprehension, the method may be illustrated with the working flow shown in
According to some embodiments, implementation of the first type of blocks and/or implementation of the second type of blocks may vary. For example, the first type of blocks may comprise the group of SLC blocks, and the second type of blocks may comprise a group of quadruple level cell (QLC) blocks, where the first bit count BITCNT(1) and the second bit count BITCNT(2) may be equal to one and four, respectively. For another example, the first type of blocks may comprise the group of SLC blocks, and the second type of blocks may comprise a group of multiple level cell (MLC) blocks, where the first bit count BITCNT(1) may be equal to one, and the second bit count BITCNT(2) may be equal to or greater than two (e.g. depending on different viewpoints regarding MLC). In some examples, the first type of blocks may comprise the group of SLC blocks, and the second type of blocks may comprise any group of multiple groups of higher level cell blocks, and the multiple groups of higher level cell blocks may comprise the group of MLC blocks, and more particularly, may comprise the group of TLC blocks, the group of QLC blocks, etc., where the first bit count BITCNT(1) may be equal to one, and the second bit count BITCNT(2) may be equal to the corresponding bit count selected from a sequence of {2, 3, 4, . . . }. In some other examples, the first type of blocks may comprise a first group in a series of groups comprising the group of SLC blocks, the group of MLC blocks, the group of TLC blocks, the group of QLC blocks, etc., and the second type of blocks may comprise a second group in the series of groups, such as one of the subsequent groups coming after the first group in the series of groups, where the first bit count BITCNT(1) may be equal to a certain bit count selected from a sequence {1, 2, 3, 4, . . . } corresponding to the series of groups, and the second bit count BITCNT(2) may be equal to another bit count selected from the sequence {1, 2, 3, 4, . . . } and is greater than the first bit count BITCNT(1).
In Step S22, in response to the repeated writing condition being satisfied, the memory controller 110 may store the set of data into the aforementioned at least one first type block of the first type of blocks within the NV memory 120, for performing the data storage enhancement processing. For example, the operation of Step S22 may be executed in response to the first determination result.
In Step S24, the memory controller 110 may determine whether the management table 120MT corresponding to the data storage enhancement processing is full, for managing a first storage pool within the NV memory 120 for the data storage enhancement processing, where the first storage pool may comprise at least one portion (e.g. a portion or all) of the first type of blocks within the NV memory 120, and table contents of the management table 120MT may correspond to the aforementioned at least one portion of the first type of blocks, and more particularly, may represent the aforementioned at least one portion of the first type of blocks, but the present invention is not limited thereto. If Yes, the memory controller 110 may execute Step S26; If No, the memory controller 110 may execute Step S28.
In Step S26, in response to the management table 120MT being full, the memory controller 110 may obtain at least one set of previous data (e.g. one or more sets of previous data) from one or more old members of the first storage pool, store the aforementioned at least one set of previous data into one or more second type blocks of the second type of blocks, and remove block information (e.g. one or more physical addresses) of the one or more old members from the management table 120MT, to purge the one or more old members from the first storage pool, where the one or more old members may represent one or more first type blocks of the first type of blocks.
In Step S28, the memory controller 110 may record block information (e.g. at least one physical address) of the aforementioned at least one first type block of the first type of blocks into the management table 120MT, to identify the aforementioned at least one first type block of the first type of blocks as at least one member of the first storage pool.
Based on the working flow shown in
For better comprehension, the method (more particularly, the data storage enhancement procedure) may be illustrated with the working flow shown in
According to some embodiments, the memory controller 110 may utilize the first block pool corresponding to the first type of blocks (e.g. an SLC pool corresponding to the group of SLC blocks) to perform the data storage enhancement processing mentioned in Step S20, where data stored in any block of the first block pool is protected by the data storage enhancement processing, and data stored in any block of a second block pool corresponding to the second type of blocks (e.g. a TLC pool corresponding to the group of TLC blocks, a QLC pool corresponding to the group of QLC blocks, etc.) is not protected by the data storage enhancement processing, but the present invention is not limited thereto.
Some implementation details regarding the repeated writing condition mentioned in Step S14 may be described as follows. According to some embodiments, in a situation where the command mentioned in Step S10 represents the write command and Steps S12 and S14 are entered subsequently, the memory controller 110 may perform an additional check regarding the set of data to guarantee the correctness of the operation of Step S14. In Step S14, the memory controller 110 may further perform a repeated data detection regarding the set of data to generate a repeated data detection result, where the repeated data detection result may indicate whether this set of data to be written as requested by this write command is the same as previously written data such as the data that has been written as requested by the previous write command. For example, when this write command is the next write command of the previous write command and indicates that writing data (e.g. the set of data) of the same length at the same address (e.g. the same logical address) is required, and the repeated data detection result indicates that this set of data to be written as requested by this write command is the same as the previously written data (e.g. the data that has been written as requested by the previous write command), the memory controller 110 may determine that the repeated writing condition is satisfied, and therefore Step S20 is entered; otherwise, the memory controller 110 may determine that the repeated writing condition is not satisfied, and therefore Step S30 is entered. As a result, the repeated writing condition may further comprise the repeated data detection result indicating that this set of data to be written as requested by this write command is the same as the previously written data (e.g. the data that has been written as requested by the previous write command).
According to some embodiments, performing the repeated data detection may be implemented by detecting characteristic information of the set of data, such as a cyclic redundancy check (CRC) code, a hash value, etc. of the set of data. More particularly, during performing the repeated data detection, the memory controller 110 may detect the characteristic information of the set of data (e.g. the CRC code, the hash value, etc. thereof), and compare the characteristic information of the set of data with previous characteristic information to determine whether the characteristic information of the set of data is the same as the previous characteristic information, to generate the repeated data detection result. For example, the memory controller 110 may temporarily store characteristic information of the previously written data (e.g. a CRC code, a hash value, etc. of the data of the previous write command) in the buffer memory 116 in advance to be the previous characteristic information, but the present invention is not limited thereto. For another example, the memory controller 110 may temporarily store the characteristic information of the previously written data (e.g. the CRC code, the hash value, etc. of the data of the previous write command) in any other memory of the memory device 100 to be the previous characteristic information. For yet another example, the memory controller 110 may read the characteristic information of the previously written data (e.g. the CRC code, the hash value, etc. of the data of the previous write command) from the NV memory 120 to be the previous characteristic information.
According to some embodiments, the memory controller 110 may calculate the characteristic information of the set of data (e.g. the CRC code, the hash value, etc. thereof) and the previous characteristic information (e.g. the CRC code, the hash value, etc. of the data of the previous write command) by itself, but the present invention is not limited thereto. In some embodiments, the host system 20 (e.g. the host device 50) may calculate the characteristic information of the set of data (e.g. the CRC code, the hash value, etc. thereof) and the previous characteristic information (e.g. the CRC code, the hash value, etc. of the data of the previous write command) in advance and send them to the memory device 100, for example, to be attached information of the respective data, and therefore, the memory controller 110 may obtain the characteristic information of the set of data and the previous characteristic information.
According to some embodiments, performing the repeated data detection may be implemented by comparing the set of data with the previously written data. For example, the memory controller 110 may compare the set of data to be written as requested by the write command (e.g. the current write command) with the previously written data, where the previously written data may be still buffered in a certain buffer of the memory device 100, where this buffer may be implemented with an external memory of the memory controller 110, such as a dynamic RAM (DRAM) in the memory device 100, but the present invention is not limited thereto.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
