The present invention relates to any DC circuit that can pass an electrical current through, verified, and analyzed using such techniques and monitoring attributes of degradation to predict future failure terms of the circuit.
Typical electrical circuits either operate normally, or the fail (On or Off). The wiring within these systems is typically the greatest potential for failure, and troubleshooting these system defects is both time consuming and expensive. Intermittent type failures may lead to damaged components, and extreme operator frustration. This type of failure mode is most common in automotive, aircraft, and other industrial or transportation systems. We will focus this new technology on these, with direct current (DC) systems that operate from batteries or other power supplies.
The technology is designed to use the existing power source to predict failures prior to their failed condition or during intermittent defect mode. While these systems are not being utilized to operate the equipment, a series of DC pulses (
Typical failure modes of oxidation, moisture, faulty connections, internal damage, and external destruction can be determined before the system fails, before the human vision will detect, or before existing diagnostics can provide feedback.
The present invention provides a method to predict the life expectance of DC circuits by monitoring circuit paths and sub branches for degradation.
Past prior art has provided only the means to determine a good circuit or a bad (failed) circuit. These no/no-go methods of testing provide no means to prevent a catastrophic failure or predict terms of life expectance.
The inventive method of monitoring the condition of the circuit comprises of establishing a known baseline signal for a specific type of circuit (each is somewhat different) and defining these characteristics in terms of the lead and trailing edge angular components (@ zero crossing point), the voltage (amplitude), and the period (time length) of the waveform. Ideally the angular component of the square wave should be vertical, or at 90 degrees to x-axis (
The DC pulse that is generated will be specifically tuned for the circuit under test. The DC pulse will be both of positive (V+) and negative (V−) voltage such that they are equal with respect to each other. The durations of these pulses are variable (Tv) of time but tuned to the components of the circuit. Once these pulse characteristics are established, they are mapped and stored as ‘normal’ conditions.
Successive tests utilized the identical pulse characteristics (V+, V−, and Tv) established during ‘normal’ conditions. These tests are conducted while the system is in non-operation, so as not to affect the system operation and at a predetermined interval based upon manufacturers' recommendations. The successive test pulse characteristics are compared to the “normal” conditions and prior test through the algorithm to determine rate of decay of circuit wiring. The algorithm is designed to predict the failure potential of any circuit, and approximate location of the failure point within the wire harness.
This invention provides the methods and apparatus to provide real-time predictive means to user for practicing cost effective preventive maintenance. The apparatus and inclusive communication network allow for these critical decisions to be transferred to centralized decision point.
The present invention provides the apparatus and method to measure each of the critical components of a DC circuit, provide combined attribute investigation, complete Time to Failure TTF predictive analysis, and report to remote centralized logistic system for decision process.
With reference to
A memory storage device 105, either common to load or installed as part of upgrade has the ability to store last DC pulse signal 204 for transmission when the circuit is deactivated along the identical wiring harness used for normal system operation.
In a preferred embodiment, synchronized collection of data of the Positive (V+) Leading edge (L1@N+, L2@N+, . . . , L1+y@N+), Negative (V−) Leading edge (L1@N−, L2@N−, . . . , L1+y@N−), Positive (V+) Trailing edge (T1@N+), T2@N+, . . . , T1+y@N+), Negative (V−) trailing edge (T1@N−, T2@N−, . . . , T1+y@N−), Positive (V+) voltage (dV1@N+, dV2@N+, dV1+y@N+), Negative (V−) voltage (dV1@N−, dV2@N−, dV1+y@N−); as well as the number of pulses (1+y) and the DC pulse lengths (Tv1, Tv2, . . . , Tv(1+y)) is retained for each specific circuit under review. The CPU 104 processes the information by hardware, firmware, software or a hybrid combination of these methods as described within. The initial alternating DC pulse signal 203 is compared to the latest DC pulse signal 203 by utilizing the data points described above and a customized algorithm for the circuit under review. The above analysis methodology may be completed by purely analog methods, or a combination of analog and digital methods which achieve the same or similar results.
The DC pulse signal 203 can be generated with an external power source. The DC pulse signal 203, 204 is transmitted while the circuit under test 303 is in an idle state so not to effect normal operations. The generate DC pulse train 203 is specifically tuned to the circuit under analysis and considers the specific components, materials, length, and construction of this individual circuit.
At some time period (P1), these same data points are collected (
The decay rate algorithm is based upon the angular component of the Positive (V+) Leading edge (L1@N+, L2@N+, . . . , L1+y@N+), Negative (V−) Leading edge (L1@N−, L2@N−, . . . , L1+y@N−), Positive (V+) trailing edge (T1@N+, T2@N+, . . . , T1+y@N+), Negative (V−) trailing edge (T1@N−, T2@N−, . . . , T1+y@N−) and Positive (V+) voltage (dV1@N+, dV2@N+, dV1+y@N+), Negative (V−) voltage (dV1@N−, dV2@N−, dV1+y@N−); as well as the number of pulses (1+y) and the DC pulse lengths (Tv1, Tv2, . . . , Tv(1+y)) ratios calculated each measurement cycle when compared to the original state and previous measurement cycle. The algorithm ratios each of the characteristic data set to eliminate abnormalities associate with the components of the DC circuit under review, as these can produce false-positives in the decay curve analysis.
Typical DC circuit ratios may be reflected as such;
EDGE RATIO=Sine(T1@N+−T1@P1+)−Sine(L1@N+−L1@P1+)+Sine(T1@N−−T1@P1−)−Sine(L1@N−−L1@P1−)+Sine(T2@N+−T2@P1+)−Sine(L2@N+−L2@P1+)+Sine(T2@N−−T2@P1−)−Sine(L2@N−−L2@P1−)+ . . . +Sine(T1+y@N+−T1+y@P1+)−Sine(L1+y@N+−L1+y@P1+)+Sine(T1+y@N−−T1+y@P1−)−Sine(L1+y@N−−L1+y@P1−)
PERIOD RATIO=(Tv1@N1−Tv1@P(x−1))/2+(Tv2P(x−1)−Tv2@P(x))/2+(Tv2@N1−Tv2@P(x−1))/2+(Tv2P(x−1)−Tv2@P(x))/2+ . . . +(Tv(1+y)@N1−Tv(1+y)@P(x−1))/2+(Tv(1+y)P(x−1)−Tv(1+)@P(x))/2
AMPLITUDE RATIO=(dV1@N+[L1@N+]−dV1@N+[T1@N+]+dV1@N−[L1@N−]−dV1@N−[T1@N−])/2+(dV2@N+[L2@N+]−dV2@N+[T2@N+]+dV2@N−[L2@N−]−dV2@N−[T2@N−])/2+ . . . +(dV(1+y)@N+[L(1+y)@N+]−dV(1+y)@N+[T(1+y)@N+]+dV(1+y)@N−[L(1+y)@N−]−dV(1+y)@N−[T(1+y)@N−])/2
Multiple algorithm points can be stored for history purposes and may be useful for technical troubleshooting of system integrity.
Once an appropriate baseline is established for a specific DC circuit, a quantitative threshold may be established in order to compute the life expectance of the circuit under review. This life expectancy may be reestablished based upon future analysis and preventative maintenance actions can be scheduled based upon end of life projections.
As such, an invention has been disclosed in terms of preferred embodiments thereof which fulfills each and every one of the objects of the present invention as set forth above and provides a new and improved method and apparatus for predicting the life cycle of a DC circuit.
Of course, various changes, modifications, and alterations from the teachings of the present invention may be contemplated by those skilled in the art without departing from the intended spirit and scope thereof. It is intended that the present invention only be limited by the terms of the appended claim.
Filing Document | Filing Date | Country | Kind |
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PCT/US2017/061957 | 11/16/2017 | WO | 00 |
Publishing Document | Publishing Date | Country | Kind |
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WO2018/094006 | 5/24/2018 | WO | A |
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