Patent Application
20070118837
The present invention relates generally to the data processing field, and more particularly, relates to a method, and apparatus for preventing livelocks in processor selection of load requests in a multiprocessor (MP) system.
Improved computer system performance advantageously is achieved with a multiprocessor (MP) computer system. Multiprocessing computer systems include multiple processors, each processor employed to perform computing tasks. A particular computing task may be performed upon one processor while other processors perform other unrelated computing tasks. Alternatively, components of a particular computing task are distributed among the multiple processors to decrease the time required to perform the computing task as a whole.
One commercially available multiprocessing computer system is a symmetric multiprocessor (SMP) system. An SMP computer system typically includes multiple processors connected through a cache hierarchy to a shared bus. A memory connected to the shared bus is shared among the processors in the system. All processors within an SMP computer system have symmetric access to all resources within the system.
When selecting requests from multiple processors a livelock condition can occur whereby one processor cannot make forward process because one or more of the other processors are consuming all of the available resources or bandwidth. Selection mechanisms such as round-robin or least-recently-used schemes can eliminate part of the problem but further livelocks can exist where the arrival time of requests play a role.
For an example, consider a round robin selection where Round robin points to a first processor P0, and processor P0 wins. Round robin advances to a next processor P1, and processor P1 wins. Round robin advances to next processor P2, and processor P2 wins but is retried because resources are busy with processors P0 and P1. Round robin then advances to first processor P0, and processor P0 wins, and continues forever with processors P0 and P1 winning. In this case processor P2 never gets through and hangs.
A need exists for an effective mechanism to enable processing of load requests in a multiprocessor (MP) computer system while preventing livelocks.
A principal aspect of the present invention is to provide a method, and apparatus for preventing livelocks in processor selection of load requests in a multiprocessor (MP) system. Other important aspects of the present invention are to provide such method, and apparatus for preventing livelocks in processor selection of load requests in a multiprocessor (MP) system substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method, and apparatus are provided for preventing livelocks in processor selection of load requests in a multiprocessor (MP) system. On random occasions a selection mechanism is changed for first holding up all requests and then a random selection is made. Then a round robin selection mechanism is used for further requests.
In accordance with features of the invention, a livelock-preventing selection mechanism is configurable to change the duration of the random selection so that performance degradation due to holding up requests is minimized. The livelock-preventing selection mechanism includes a pair of linear feedback shift registers (LFSRs), each LFSR generates pseudo random values.
In accordance with features of the invention, the random occasions the selection mechanism is changed is determined based upon a first one of the LFSRs and the random selection is determined based upon a second one of the LFSRs. The duration of the random selection is determined based upon the second one of the LFSRs.
The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:
In accordance with features of the invention, a method for preventing livelocks in processor selection of load requests uses a pair of linear feedback shift registers (LFSRs). Each LFSR generates pseudo random values used along with a round robin selection mechanism that normally selects requests in a round robin fashion. On random occasions determined by one of the LFSRs the selection mechanism is changed by first holding up all requests in order to allow each processor time to re-establish retried requests and then a random selection is made. Then the normally active round robin selection mechanism takes over for further requests. This livelock-preventing mechanism is configurable to change the duration of the random selection so that performance degradation due to holding up requests is minimized.
Having reference now to the drawings, in
Multiprocessor system 100 includes a respective multiplexer 110, MUX0, MUX1, MUX2. Each respective multiplexer 110, MUX0, MUX1, MUX2 is coupled to the output of the respective associated pre-queue register 106, PRE-Q0, PRE-Q1, PRE-Q2 and is coupled to the respective associated queue 108, QUEUE 0, QUEUE 1, QUEUE 2. Each respective multiplexer 110, MUX0, MUX1, MUX2 is, for example, a 9:1 multiplexer with the illustrated 8-stage queue 108.
Multiprocessor system 100 includes a respective post-queue register 112, POST-Q0, POST-Q1, POST-Q2 coupled to the output of the respective associated multiplexer 110, MUX0, MUX1, MUX2. A respective multiplexer 114, MUX0, MUX1, MUX2 is coupled to the respective associated post-queue register 112 and respective associated instruction register 104 IN_REQ0, IN_REQ1, and IN_REQ2 that provides a processor load queue bypass.
Each multiplexer 114, MUX0, MUX1, MUX2 is a 2:1 multiplexer. The output of multiplexers 114, MUX0, MUX1, MUX2 are applied to a selection multiplexer 116, MUX0, MUX1, MUX2 that receives the processor control selection signals P0 OLDEST, P1 OLDEST AND P2 OLDEST. Livelock-preventing select logic apparatus 200 illustrated and described with respect to
In accordance with features of the invention, requests are allowed to be selected continuously as long as L2 _ARB_EN is active. Otherwise, when an inactive L_ARB_EN is applied to the register 118, requests are held back where they can collect in the load queues 108 and the selection logic has no effect until L2_ARB_EN returns active. Processor selection is handled by the 1-hot selection signals P0 OLDEST, P1 OLDEST AND P2 OLDEST applied to multiplexer 116. These are normally updated in a round robin manner but are randomly chosen when the livelock logic controls selection P0 OLDEST, P1 OLDEST AND P2 OLDEST, as illustrated and described with respect to
Referring now to
In accordance with features of the invention, livelock-preventing select logic apparatus 200 is driven by LFSRs and randomly invoked to hold up requests from all processors generating control signal L2_ARB_EN and then make a random processor selection via signals P0 OLDEST, P1 OLDEST and P2 OLDEST.
Selection logic apparatus 200 includes a first LFSR 202 coupled to a pulse generator 204. A counter 206, such as a 11-bit counter, has an output feedback +1 208 applied to a first input of a multiplexer MUX 210 with a 0 applied to another input of MUX 210. Counter 206 provides a second input to the pulse generator 204. The pulse generator 204 that generates a pulse at a programmable interval, such as 512, 1K or 2K cycles together with a plus or a minus random offset determined based upon a value applied by the first LFSR 202 at an output node labeled CTR_EXP.
Referring also to
The pulse output of pulse generator 204 at node CTR_EXP provides a control input to the first LFSR 202, an input to a count down counter 210, for example, starting from 0-15. A second LFSR 212 is coupled to the count down counter 210, which generates an output CNT_EXPIRED. The output CNT_EXPIRED and a switchable livelock enable signal inverted by an inverter 214 are applied to an OR gate 220. The switchable livelock enable signal CHK SWITCH LIVE-LOCK ENABLE optionally is provided for disabling the livelock-preventing select logic apparatus 200, and allowing the round-robin selection mechanism to exclusively be used, if desired. The ORed output and an L2 signal to allow load requests V_QS_ID_PRE_ARB_VAL are applied to an AND gate 222. The ANDed output is applied to an existing 2 GHz register 224, for example, where the clock speed of the logic 200 is 2 GHz, for generating the control signal L2_ARB_EN.
Referring again to
Referring to
The 1-hot selection signal P0 OLDEST, P1 OLDEST or P2 OLDEST is applied to multiplexer 116 in
While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.
