Karl L. Wang et al., "A 21-ns 32K.times.8 CMOS Static RAM with a Selectively Pumped p-Well Array", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, pp. 704-711, (Oct. 1987). |
Larry F. Childs and Ryan T. Hirose, "An 18 ns 4K.times.4 CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, pp. 545-551, (Oct. 1984). |
Katsuro Sasaki et al., "A 15-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. SC-23, No. 5, pp. 1067, 1069-1072, (Oct. 1988). |
Takayasu Sakurai et al., "A Low Power 46 ns 256 kbit CMOS Static RAM with Dynamic Double Word Line", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, pp. 578-585, (Oct. 1984). |
Cheng-Wei Chen et al., "A Fast 32K.times.8 CMOS Static RAM with Address Transition Detection", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 4, pp. 533-537, (Aug. 1987). |