Patent Application
20060039284
The present invention pertains to communicating data. More particularly, the present invention relates to a method and apparatus for processing a complete burst of data bursty data.
A wide variety of electronic communication systems utilize an interface known as a “bursty interface”. A bursty interface is an interface that is generally capable of sending or receiving some amount of data on a periodic basis. During a first interval in such a period, data is usually sent or received at a high data rate. During a second interval within the same period, the interface is generally quiescent, i.e. the interface is not sending or receiving data during this second interval.
Bursty interfaces are commonly used because of the bursty nature of data communicated from one system to another. Bursty interfaces are also commonly used as a mechanism for decoupling the physical sampling of data between two systems that are communicatively coupled to each other. In digital systems, for example, two independent systems are generally operated using two independent clocks. A bursty interface is a practical means to enable the transfer of data between two separately clocked systems because a bursty interface generally provides an elasticity buffering capability.
In the past, a bursty interface was generally designed around a linear memory known as a “first-in-first-out” (FIFO) memory. A FIFO memory generally provides an input port and an output port. In many implementations, the input port and the output port can be independently clocked. For example, an independent clocking mechanism is generally provided for a FIFO input port. Using this independent clocking mechanism, data can be stored in the FIFO memory without regard to any clocking mechanism used to retrieve data from the FIFO. It generally follows that a FIFO memory provides a separate and independent clocking mechanism for data retrieval. The retrieval clocking mechanism can be used without regard to the clock mechanism used to store data in the FIFO memory. This type of structure can be used to support a simplistic mechanism for decoupling the clock signals of two independent data systems.
In a bursty interface, the input port of a FIFO has traditionally been used to receive data during a first interval by means of an input clocking mechanism. The output port of the FIFO can then be used to retrieve data using an independent retrieval clocking mechanism. The retrieval clocking mechanism is also generally used as a basis for manipulating data within the system receiving bursty data. As such, the retrieval clocking mechanism can be considered the operating clock that synchronizes the internal operation of the system receiving such bursty data. Data can then be retrieved from the output port of the FIFO at some convenient rate commensurate with the operation of the system receiving the bursty data. Bursty data can then be stored in the FIFO as it arrives at an independent rate from another system.
Modern computer networking systems are also employing bursty interface structures. For example, one common computer networking system known as System Packet Interface (SPI) comprises a specific implementation of a bursty interface that can be used to transfer data packets from one system element to another. The SPI interface has been defined at various levels (e.g. SPI-3 and SPI-4). SPI-3 and SPIA define various aspects of the System Packet Interface including but not limited to transfer speed, packet sizing and burst sizing. One interesting characteristic in any bursty interface used to carry data packets is that of packet alignment relative to a data burst. For example, a data burst may be used to carry a complete single packet, a portion of a single packet, a complete single packet and a portion of a second packet, two or more complete data packets and portions of two or more data packets. Alignment of a data packet to a data burst is a common issue irrespective of the type of bursty interface used to communicate a data packet from one system to another.
Although a FIFO is a useful building block in the design and implementation of a bursty interface, there are several problems that surface when a bursty interface is used to convey a data packet. One specific problem is that of flow control. When a bursty interface is based on a FIFO, flow control is generally designed to reflect the availability of memory within the FIFO. For example, when a FIFO is filled to a certain capacity, the FIFO may not be able to reliably receive an entire burst of data. Accordingly, a system that is delivering bursty data to a receiving system is directed to hold additional data transfers until the receiving system can retrieve some of the data stored in the FIFO. As the receiving system retrieves data stored in the FIFO, the hold directive can be suspended once the FIFO can again reliably accommodate an additional burst of data. Although such flow control can be used to manage a FIFO-based bursty interface, it is simply not suitable when the data carried by a data burst is packetized. This is because a hold directive can be issued during a data burst, preventing the reception of an entire data burst within a given period of time. If the FIFO cannot reliably accommodate an entire data burst, a receiving system may not be able to properly process a data packet if the data packet is only partially received by the FIFO. This is especially problematic in the event that a data packet needs to be forwarded to another system using a second bursty interface.
Several alternative embodiments will hereinafter be described in conjunction with the appended drawings and figures, wherein like numerals denote like elements, and in which:
Bursty interfaces are often used to receive packetized data. One example of a packetized data interface is the System Packet Interface (SPI). The SPI interface is primarily defined in two documents including:
Although the present method and apparatus can be used to process packetized data bursts that conform to the SPI specification, the claims appended hereto are not intended to be limited in scope to such applications and the present method and apparatus can be applied in any application where bursty data from one system is received in another system.
Also included in various example alternative embodiments of the system 205 are one or more functional modules. A functional module is typically embodied as an instruction sequence. An instruction sequence that implements a functional module, according to one alternative embodiment, is stored in the memory 235. The reader is advised that the term “minimally causes the processor” and variants thereof is intended to serve as an open-ended enumeration of functions performed by the processor 200 as it executes a particular functional module (i.e. instruction sequence). As such, an embodiment where a particular functional module causes the processor 200 to perform functions in addition to those defined in the appended claims is to be included in the scope of the claims appended hereto. This example embodiment further includes a burst receiver module 240 and a burst dispatch module 245, both of which are stored in the memory 235. In yet another alternative example embodiment, the memory 235 is also use to store one or more logical channel tables 250. In yet another alternative example embodiment, the memory 235 is used to store one or more burst buffers (255,260), which are logically equivalent to a memory segment described supra.
The functional modules (i.e. their corresponding instruction sequences) described thus far that enable processing of a burst of data according to the present method are, according to one alternative embodiment, imparted onto computer readable medium. Examples of such medium include, but are not limited to, random access memory, read-only memory (ROM), compact disk ROM (CD ROM), floppy disks, hard disk drives, magnetic tape and digital versatile disks (DVD). Such computer readable medium, which alone or in combination can constitute a stand-alone product, can be used to convert a general-purpose computing platform into a device capable of processing a burst of data according to the techniques and teachings presented herein. Accordingly, the claims appended hereto are to include such computer readable medium imparted with such instruction sequences that enable execution of the present method and all of the teachings herein described.
Once a complete burst of data stored is stored in the memory 235, the processor 200 then executes the burst dispatch module 245. When executed by the processor, the burst dispatch module 245 minimally causes the processor to retrieve 247 from the memory 235 one or more complete bursts of data. The burst dispatch module 245 then minimally causes the processor to generate an egress burst according to the one or more bursts of data retrieved 247 from the memory. The egress burst of data is then directed 232 to the egress interface 230.
In one alternative example embodiment, the burst receiver module 240 causes the processor 200 to monitor the availability of memory 235 and also further minimally causes the processor to generate a backpressure indicator 215 when the amount of available memory falls below a pre-established threshold. The back pressure indicator 215 is directed to the ingress interface 225, which causes a source of a burst of data to throttle delivery of said burst of data.
In yet another alternative example embodiment, the burst receiver module 240 causes the processor 200 to store a complete burst of data in the memory 235 by minimally causing the processor to allocate a first segment in the memory and then store a first complete burst of data in the allocated first segment. It should be appreciated that a first segment is also referred to as a burst buffer 255.
In yet another example alternative embodiment, the burst receiver module 240 causes the processor 200 to store a complete burst of data in the memory 235 by minimally causing the processor 200 to allocate a first segment in the memory, store a first portion of the complete burst of data in the first allocated segment, allocate a second segment (such as a second burst buffer 260) and then store a further portion of the complete burst of data in the second segment commensurate with the teachings of the present method.
In one alternative example embodiment, the burst receiver module 200 causes the processor 200 to store a complete burst of data in the memory by creating a reference to a burst buffer (255, 260) and then storing the reference (257, 262) in a logical channel table 250, which is stored in the memory 235. It should be appreciated that the logical channel table 250 is organized as a chain of references to individual burst buffers (i.e. memory segments) stored in the memory 235. According to one alternative example embodiment, the logical channel table 250 is also used to store egress burst information 252. This egress burst information 252 is typically associated with an egress data burst, which is generated by the processor 200 as it continues to execute the burst dispatch module 245.
According to one alternative example embodiment, the burst dispatch module 245, when executed by the processor 200, causes the processor to dispatch an egress burst of data by minimally causing the processor 200 to receive a back pressure indicator 231 from the egress interface 230. The burst dispatch module 245 further minimally causes the processor 200 to direct 232 to the egress interface 230 an egress burst of data retrieved 247 from the memory 235. This alternative example embodiment of a burst dispatch module 245 causes the processor 200 to direct 232 the egress burst of data to the egress interface 230 when the back pressure indicator 231 indicates that the egress interface 230 can receive a complete burst of egress data.
In yet another alternative example embodiment, the burst dispatch module 245 causes the processor 200 to dispatch an egress burst of data by minimally causing the processor 200 to retrieve egress burst information from the memory 235. In one alternative example embodiment, the burst dispatch module 245 causes the processor 200 to retrieve egress burst information from a logical channel table 250 that includes such egress burst information 252. This example embodiment of a burst dispatch module 245 further minimally causes the processor to retrieve from the memory 235 a portion of a complete burst of data. According to one alternative example embodiment, the burst dispatch module 245 causes the processor 200 to retrieve a portion of a complete burst of data by retrieving a reference (257, 262) from a logical channel table 250. The processor 200 then uses a retrieved reference (i.e. a pointer) to access a burst buffer 255 (i.e. a segment of memory) from whence a portion of a complete burst of data is retrieved.
According to yet another alternative example embodiment, the burst dispatch module 245 causes the processor 200 to dispatch an egress burst of data by minimally causing the processor 200 to retrieve egress burst information from the memory 235. As heretofore described, one alternative example embodiment of a burst dispatch module 245 causes the processor 200 to retrieve egress burst information from a logical channel table 250, which includes egress burst information 252 stored therein. According to this alternative example embodiment, the burst dispatch module 245 causes the processor 200 to then retrieve from the memory 235 a complete burst of data. In one alternative example embodiment, the burst dispatch module 245 causes the processor to retrieve a complete burst of data from the memory 235 by minimally causing the processor 200 to retrieve a reference (257, 262) from the logical channel table 250. The processor 200 then uses a retrieved reference (257, 262) to access a burst buffer (255, 260) which is also stored in memory and used to store a complete burst of ingress data.
In one additional example alternative embodiment, the burst dispatch module 245 causes the processor to dispatch an egress burst of data by minimally causing the processor 200 to retrieve egress burst information from the memory 235, which according to one alternative embodiment is retrieved from a logical channel table 250 that includes such egress burst information 252. The burst dispatch module 245 further minimally causes the processor to retrieved 247 from the memory 235 a first complete burst of data and at least one of a second complete burst of data and a portion of a second complete burst of data. It should be appreciated that, according to yet another alternative example embodiment, the burst dispatch module 245 minimally causes the processor to retrieve data from the memory by means of a reference (257, 262) which is stored in a logical channel table 250.
In yet another example embodiment, the ingress interface 225 receives an input from a source such as 621, and the egress interface 230 provides an output to a destination such as 631. Burst receiver module 240 may receive information 221 on egress burst size 223 and is capable of receiving a status signal 220 from the egress interface 230.
In all of these example alternative embodiment, the burst dispatch module 245 causes the processor 200 to generate an egress burst of data according to egress burst information retrieved 247 from the memory 235 and also according to at least one of a portion of a complete burst of data, a complete burst of data, a complete burst of data augmented with at least one of a portion of a second burst of data or a complete second burst of data. The egress burst of data generated by the processor as it executes the burst dispatch module 245 is then conveyed to 232 to the egress interface 230.
The transmit burst unit 315 retrieves one or more bursts of data from a memory 330, again according to a logical channel association, by using a memory address provided by the memory control unit 310. The transmit burst unit 315 retrieves burst data using a read interface 345 that is included in the memory interface 347 provided by the burst data interface controller 320. The transmit burst unit 315 then directs burst data to an egress interface 325.
In an alternative example embodiment, the memory control unit 310 monitors the availability of memory in an external memory resource 330. Based on the availability of memory, the memory control unit 310 generates a back pressure indicator 307. The back pressure indicator 307, when active, indicates that the memory 330 can not accommodate a complete burst of ingress data. Accordingly, the back pressure indicator 307 can be used by an ingress interface 300 in order to throttle the delivery of a complete burst of data to the burst data interface controller 320.
In one alternative example embodiment, a memory control unit 310 includes one or more logical channel units (365, 367,370). A logical channel unit 365, which according to one alternative embodiment, comprises a first-in-first-out (FIFO) memory device. The logical channel unit 365 is used to store a reference to an available segment of memory received from the available segment unit 360. When a reference to an available segment is provided by the available segment unit 360, the logical channel unit 365 captures the reference and also directs the captured reference to a segment identifier 390 portion of the address unit 393. The segment identifier portion 390 of the address unit then uses the segment reference in conjunction with a counter 395 to generate an access address 340 as the receive burst unit 305 stores a complete burst of data in successive location in an external memory resource 330. It should be appreciated that where a particular complete burst of data is larger than a particular memory segment, an additional segment reference is provided by the available segment unit 360 and directed to the logical channel unit 365. The logical channel unit 365 makes the second memory segment reference available to the segment identifier portion 390 of the address unit 393. In this manner, a complete burst of data is allowed to span a plurality of memory segments stored in an external memory resource 330.
In operation, an ingress request decoder 380 included in one alternative example embodiment of a memory control unit 310 receives a logical channel identifier 350 from the receive burst unit 305. The ingress request decoder 380 then selects a particular logical channel unit 365 according to the logical channel identifier 350 received from the receive burst unit 305. The ingress request decoder 380 also generates a grant signal back to the receive burst unit 305, which indicates to the receive burst unit 305 that it is able to store a complete burst of memory in an external memory resource 330.
It should be appreciated that various alternative example embodiments of a memory control unit 310 include one or more burst information pointers (366,368, 371). Typically, a burst information pointer is associated with the particular logical channel unit (365,367,370). The burst information pointer is used to access a segment in an external memory resource 330 that is used to store egress burst information for a particular logical channel. Accordingly, various alternative example embodiments of a burst data interface controller 320 will use the contents of the burst information pointer to enable the transmit burst unit 315 to retrieve an egress burst information from an external memory resource 330.
In one alternative example embodiment, for example, the transmit burst unit 315 retrieves from an external memory resource 330 egress burst information according to a memory access address 340 provided by the memory control unit. A special burst information request signal 311 is used by the transmit burst unit 315 to distinguish a request signal 355 that is otherwise conveyed from the transmit burst unit 315 to the memory control unit 310 when the transmit burst unit 315 needs to retrieve burst data from an external memory 330.
In one alternative example embodiment, the transmit burst unit 315 retrieves a portion of a complete data packet from an external memory resource 330 by directing a request 355 to the memory control unit 310. The memory control unit 310 then generates a memory access address 340, which is used by the transmit burst unit 315 to access a portion of an egress burst of data stored in an external memory resource 330 using the read interface 345 included in the memory interface 347 provided by the burst data interface controller 320. It should be appreciated that once a memory segment referenced by a segment reference stored in a logical channel unit 370 is exhausted (i.e. all of the data has been retrieved by the transmit burst unit 315), the segment reference stored in the logical channel unit is returned back to the available segment unit 360. This frees the memory segment and allows it to be allocated to a different logical channel unit at a subsequent point in time. It should also be appreciated that a segment reference will not be returned to the available segment unit 360 until all of the data stored in the memory segment is retrieved from the external memory resource 330.
In one alternative example embodiment, the memory control unit 310 provides one or more memory access addresses 340 so as to enable the transmit burst unit 315 to retrieve a complete burst of data from an external memory resource 330. In yet another alternative example embodiment, a memory control unit 310 provides a first set of one or more memory access addresses 340 in order to enable the transmit burst unit 315 to either retrieve a portion of a second complete burst of data stored in the external memory 330 or to retrieve a second complete burst of data stored in the external memory 330.
In all of these example embodiments, the transmit burst unit 315 generates an egress burst of data according to egress burst information retrieved from the memory 330 and further according to burst data retrieved from the memory 330 as heretofore described. The transmit burst unit 315 then directs the egress burst of data to an egress interface 325.
While the present method and apparatus has been described in terms of several alternative and exemplary embodiments, it is contemplated that alternatives, modifications, permutations, and equivalents thereof will become apparent to those skilled in the art upon a reading of the specification and study of the drawings. It is therefore intended that the true spirit and scope of the claims appended hereto include all such alternatives, modifications, permutations, and equivalents.
This patent application claims priority of U.S. Application Ser. No. 60/561,774 filed on Apr. 12, 2004, entitled “Method And Apparatus For Forwarding Bursty Data”, which is by the same inventors as this application and which is hereby incorporated herein by reference. This patent application claims priority of U.S. application Ser. No. 10/861,879 filed on Jun. 4, 2004, entitled “Method And Apparatus For Forwarding Bursty Data”, which is by the same inventors as this application and which is hereby incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 60561774 | Apr 2004 | US |
