This invention relates to Serial Advanced Technology Attachment (SATA) input/output (I/O) assemblies.
The Parallel ATA (Advanced Technology Attachment) specification has defined the standard storage interface for PCs since the early 1980s. Parallel ATA provides low cost, broad operating system support, and steady evolution. Over time, parallel ATA has continuously evolved to support higher speed and performance. However, due to several reasons, including performance headroom, cabling issues, and voltage tolerance requirements, a new storage interface known as Serial ATA has recently been created.
Serial ATA may combine software transparency, low cost, scalability, and design flexibility to overcome the limitations of parallel ATA. Point-to-point data rates of 1.5 Gbps may be attainable with Serial ATA. Although SATA provides many benefits over PATA, there remains a large installed user-base of PATA compatible storage devices and computers. To continue to use the existing PATA compatible storage devices, bridge devices have been developed to interface PATA devices to SATA compatible computer systems.
In one aspect, an interface circuit for interfacing a Parallel ATA bus to a storage device. The interface circuit including a storage device controller in communication with the storage device to control a flow of information between the storage device and a Serial ATA bus. The Serial ATA bus to carry information having a Serial ATA format. A bridge circuit configured as a host bridge to interface between the Serial ATA bus and the Parallel ATA bus. The host bridge to convert Serial ATA information to Parallel ATA information and to convert Parallel ATA information to Serial ATA information.
The details of one or more embodiments of the invention are set forth in the accompa-nying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.
A hard disk controller 56 controls the flow of information between the SATA compliant bus 58 and a storage device 52. The storage device 52 may be any device for storing information such as a hard disk drive (HDD) and a CD-ROM. The hard disk controller 56 may be any type of controller that may interface to a SATA compliant bus. The SATA compliant bus 58 is suitable for carrying information that is formatted in accordance with the SATA standard.
A bridge circuit 60 is connected between the Serial ATA compliant bus 58 and the Parallel ATA compliant bus 54. The bridge circuit 60 may be selected to be in a host mode or a device mode in which the bridge circuit operates respectively as a host bridge or a device bridge. In this aspect, the bridge circuit 60 operates as a host bridge to enable the use of low-cost, widely available Parallel ATA connectivity while using a high-speed Serial ATA controller 56 to interface to the storage device 52. The bridge circuit 60 may receive Serial ATA commands communicated over the Serial ATA compliant bus 58. The bridge circuit 60 may decode the commands and convert them to Parallel ATA device commands. For responses from the Parallel ATA bus 54, the bridge circuit 60 may decipher, process, and convert the responses to Serial ATA protocol and communicate the responses over the Serial ATA compliant bus 58.
A mode select input 62 of the bridge circuit 60 may set the operating mode of the bridge circuit 60. Supported operating modes may include modes such as host mode and device mode. In host mode, the bridge circuit 60 operates as a host bridge. In device mode, the bridge circuit 60 operates as a device bridge. The mode select input 62 is preferably a single digital input and may advantageously be set at any time during the operation of the interface circuit 50. However, the mode select input 62 may also be implemented as one or more digital and analog inputs or be received via a Universal Asynchronous Receiver-Transmitter (UART).
An emulation circuit 82 may include two or more bridge circuits 84 to emulate master/slave mode for the storage devices 76. Each of the bridge circuits 84 connects between the PATA compliant bus 72 and corresponding ones of the SATA compliant buses 74. Each of the bridge circuits 84 may include a mode select input and an emulation select input.
The mode select input may receive a mode signal to set the bridge circuit 84 to either a host mode or a device mode. In this aspect, the bridge circuit 84 is preferably set to the host mode. When in host mode, the emulation select input may receive an emulation signal to set the bridge circuit 84 to an emulation state such as master, slave, and master/slave. The bridge circuit 84 emulates a storage device as a function of the emulation state indicated by the emulation signal.
The hot plug enable input 116 may receive a hot plug signal to enable or disable a hot plug mode. The bridge circuits 110 and 112 may also receive one or more of the hot plug signal and the mode signal via a communication device such as a UART. During hot plug mode, the bridge circuits may monitor the SATA compliant bus 104 to determine whether the SATA compliant bus has been disconnected or connected. For example, the bridge circuits may sense activity on the SATA compliant bus 104 to determine whether a hot plugging operation such as connecting or disconnecting has occurred.
In response to detecting a disconnecting operation, a signal may be sent to the operating system associated with the host 106 indicating that the storage device 108 has been disconnected. The bridges 110 and 112 may then monitor the SATA compliant bus 104 for activity such as an out of band (00B) sequence. If activity is detected on the SATA compliant bus 104, the operating system may be notified and the bridges 110 and 112 may independently initiate operations to establish a communication link between the host 106 and the storage device 108 such as resetting the PHY associated with each bridge 110 and 112.
A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, a UART may be included in a bridge circuit for communicating information. The UART may receive inputs such as mode select, master/slave emulation, and hot plug enable and communicate those inputs to other circuits in the bridge circuit. Accordingly, other embodiments are within the scope of the following claims.
The present disclosure is a continuation of U.S. patent application Ser. No. 11/879,108 (now U.S. Pat. No. 8,677,047), filed on Jul. 16, 2007, which is a continuation of U.S. patent application Ser. No. 10/339,897 (now U.S. Pat. No. 7,246,192), filed Jan. 10, 2003. The entire disclosures of the applications referenced above are incorporated herein by reference.
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Number | Date | Country | |
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Parent | 11879108 | Jul 2007 | US |
Child | 14215919 | US | |
Parent | 10339897 | Jan 2003 | US |
Child | 11879108 | US |