The invention relates to communications, and more particularly, to providing more particularly to channel interleaving.
Radio communication systems, such as cellular systems (e.g., spread spectrum systems (such as Code Division Multiple Access (CDMA) networks), or Time Division Multiple Access (TDMA) networks), provide users with the convenience of mobility along with a rich set of services and features. This convenience has spawned significant adoption by an ever growing number of consumers as an accepted mode of communication for business and personal uses. To promote greater adoption, the telecommunication industry, from manufacturers to service providers, has agreed at great expense and effort to develop standards for communication protocols that underlie the various services and features. One key area of effort involves broadcast and multicast services. Development of transmission standards, notably in the area of channel interleaving, has not adequately provided for such broadcast and multicast services.
Therefore, there is a need for an approach to provide a channel interleaving scheme that is optimized for broadcast and multicast services.
These and other needs are addressed by the invention, in which an approach is presented for channel interleaving in a communication system that provide, for example, broadcast and multicast services.
According to one aspect of an embodiment of the invention, a method comprises receiving a plurality of symbols. The method also comprises partitioning the symbols into a plurality of subblocks. The subblocks form a plurality of subsequences. Additionally, the method comprises generating a first output sequence from the subsequences. Further, the method comprises selecting the subsequences of the first output sequence and puncturing the first output sequence to generate a second output sequence, and interleaving the second output sequence.
According to another aspect of an embodiment of the invention, an apparatus comprises a symbol reordering module configured to receive a plurality of symbols and to partition the symbols into a plurality of subblocks. The apparatus also comprises a subblock repetition module configured to repeat the subblocks. The subblocks form a plurality of subsequences. The subblock repetition module is further configured to generate a first output sequence from the subsequences. Additionally, the apparatus comprises a sequence selection and punctuation module configured to select the subsequences of the first output sequence and to puncture the first output sequence to generate a second output sequence. Further, the apparatus comprises a matrix interleaving module configured to interleave the second output sequence.
According to another aspect of an embodiment of the invention, a method comprises encoding a plurality of signals as encoded symbols, and scrambling the encoded symbols. The method also comprises interleaving the scrambled symbols. The step of interleaving includes reordering the encoded symbols, wherein the encoded symbols are sequentially distributed into a plurality of subblocks. The step of interleaving also includes performing repetition of the subblocks, wherein the subblocks are formed into subsequences. Also, the step of interleaving includes performing selection and punctuation of the subsequences, and applying a matrix interleaving scheme to the symbols associated with the selected and punctured subsequences. Further, the method comprises modulating the interleaved symbols as modulated signals, and transmitting the modulated signals.
According to yet another aspect of an embodiment of the invention, a system comprises an encoder configured to encode a plurality of signals as encoded symbols. The system also comprises a scrambler configured to scramble the encoded symbols, and a channel interleaver configured to interleave the scrambled symbols. The channel interleaver is configured to perform the step of reordering the encoded symbols, wherein the encoded symbols are sequentially distributed into a plurality of subblocks. Additionally, the channel interleaver is configured to perform the step of performing repetition of the subblocks, wherein the subblocks are formed into subsequences. Further, the channel interleaver is configured to perform the step of performing selection and punctuation of the subsequences, and applying a matrix interleaving scheme to the symbols associated with the selected and punctured subsequences. Further, the system comprises a modulator configured to modulate the interleaved symbols as modulated signals.
Still other aspects, features, and advantages of the invention are readily apparent from the following detailed description, simply by illustrating a number of particular embodiments and implementations, including the best mode contemplated for carrying out the invention. The invention is also capable of other and different embodiments, and its several details can be modified in various obvious respects, all without departing from the spirit and scope of the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
The invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements and in which:
An apparatus, method, and software for providing channel interleaving in a communication system are described. In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It is apparent, however, to one skilled in the art that the invention may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the invention.
Although the present invention is discussed with respect to a radio communication network (such as a cellular system), it is recognized by one of ordinary skill in the art that the present invention has applicability to any type of communication systems, including wired systems. Additionally, the various embodiments of the present invention are described with respect to Turbo codes; however, it is contemplated these embodiments are applicable to other coding schemes (e.g., convolutional and/or block codes).
By way of example, a radio network operates according to the Third Generation Partnership Project 2 (3GPP2) standard for supporting High Rate Packet Data (HRPD), in particular, Enhanced Broadcast-Multicast (EBCMCS). Enhanced Broadcast-Multicast (EBCMCS) has been proposed for 1xEV-DO, which introduced Orthogonal Frequency Division Multiplexing (OFDM) modulation to combat a multi-path fading channel. The present invention, according to various embodiments, improves performance of EBCMCS systems. A more detailed description of the HRPD and EBCMCS is provided in 3GPP2 C30-20040607-060, entitled “Enhanced Broadcast-Multicast for HRPD,” June 2004; 3GPP2 C30-20040823-060, entitled “Detailed Description of the Enhanced BCMCS Transmit Waveform Description,” August 2004; and TSG-C.S0024-IS-856, entitled “cdma2000 High Rate Packet Data Air Interface Specification”; all of which are incorporated herein by reference in their entireties.
The AN 105 is a network equipment that provides data connectivity between a packet switched data network, such as the global Internet 113 and the AT 101. In cdma2000 systems, the AT 101 is equivalent to a mobile station, and the access network is equivalent to a base station.
The AN 105 communicates with a Packet Data Service Node (PDSN) 111 via a Packet Control Function (PCF) 109. Either the AN 105 or the PCF 109 provides a SC/MM (Session Control and Mobility Management) function, which among other functions includes storing of HRPD session related information, performing the terminal authentication procedure to determine whether an AT 101 should be authenticated when the AT 101 is accessing the radio network, and managing the location of the AT 101. The PCF 109 is further described in 3GPP2 A.S0001-A v2.0, entitled “3GPP2 Access Network Interfaces Interoperability Specification,” June 2001, which is incorporated herein by reference in its entirety.
In addition, the AN 105 communicates with an AN-AAA (Authentication, Authorization and Accounting entity) 107, which provides terminal authentication and authorization functions for the AN 105.
Both the CDMA2000 1xEV-DV (Evolutionary/Data and Voice) and 1X EV-DO (Evolutionary/Data Only) air interface standards specify a packet data channel for use in transporting packets of data over the air interface on the forward link and the reverse link. A wireless communication system may be designed to provide various types of services. These services may include point-to-point services, or dedicated services such as voice and packet data, whereby data is transmitted from a transmission source (e.g., a base station) to a specific recipient terminal. These services may also include point-to-multipoint (i.e., multicast) services, or broadcast services, whereby data is transmitted from a transmission source to a number of recipient terminals.
One approach for transmitting signals over the communication system 100 is to utilize a terminal with a transmit chain of
To achieve better performance, a cyclic shift re-ordering process 211 is introduced after modulation. The process of inserting guard tones are implemented next by the insertion module 213, followed by the pilot tone insertion by the pilot tone insertion module 215 into the signal.
After 16-QAM (Quadrature Amplitude Modulation) modulation, there are 240 16-QAM modulated data symbols per symbol block, which, together with 64 Quadrature Phase Shift Keying (QPSK) pilot symbols and 16 guard symbols, constitute one OFDM block with 320 tones. Following frequency domain QPSK spreading by spreader 217—attached to a Linear Feedback Shift Register (LFSR) 219 that supplies the PN sequences, Inverse Fast Fourier Transform (IFFT) time domain data symbols are obtained by the IFFT module 221.
After adding cyclic prefix (CP) by the cyclic prefix module 223 and Pseudo-Noise (PN) de-spreading using Quadrature PN dispreading module 225, time domain data symbols are time-multiplexed with the pilot and Medium Access Control (MAC) channels by multiplexer 227 in accordance with TSG-C.S0024-IS-856, with the IS-856 traffic channel being replaced by the Enhanced Broadcast Multicast (EBM) traffic channel (as detailed in C30-20040823-060).
Further, the time-multiplexed signal is slot-interlaced (if it is a multi-slot transmission), quadrature PN spread by module 229, and base-band filtered by the pulse shaping filter 231. The result signal is then transmitted over the air interface 103.
Traditionally, the scheme of channel interleaver 205 and truncation module 207 is exactly the same as that in 1xEV-DO (TSG-C.S0024-IS-856), i.e., the subblocks of systematic bits U, parity bits V0/V0′ and V1/V1′, are interleaved separately, and the truncation module 207 provides certain puncture patterns for parity bits while the systematic bits are kept and transmitted always in the first slot.
The channel interleaver 205 is designed in favor of HARQ (Incremental Redundancy) for unicast transmission. For broadcast-multicast scenario, such a constraint does not exist; the design of the channel interleaver of
The single interleaver 305 operates on both systematic and parity bits, and offering time diversity gain for systematic bits in the presence of fast fading channel as well as more interleaver gain due to the larger interleaver size. According to various embodiments, the channel interleaver 305 utilizes four stages of processing—i.e., symbol reordering, subblock repetition, sequence selection and punctuation, and matrix leaving (as shown in
In an exemplary embodiment, for Rate Set (RS) 1, 2, or 5, the output of the Turbo encoder 301 is scrambled and demultiplexed into five subblocks denoted as S, P0, P0′, P1, P1′, each of the length N (N=3072 for RS1 or RS5, N=2048 for RS2). For RS3 or 4, the output of the Turbo encoder 301 can be scrambled and demultiplexed into three subblocks denoted as S, P0, P0′; each of the length N (N=5120 for RS3, N=4096 for RS4).
In this example, a higher order modulation scheme, such as 16-QAM modulation is adapted. As such, four consecutive symbols are grouped to form a 16-QAM modulation symbol. If the required number of modulation symbols exceeds the number modulation symbols at a previous stage, the first few symbols of the modulation symbol sequence is repeated; otherwise, the output of the previous stage is truncated.
The S, P0, P1, P0′ and P1′ subblocks can form three subsequences 503, named U, V0/V0′, and V1/V1′. The subsequence U includes the subblock S; the subsequence V0/V0′ includes the subblock P0 followed by the subblock P0′; the subsequence V1/V1′ includes the subblock P1 followed by the subblock P1′.
The output sequence Soutput1 of this stage includes three subsequences: U subsequence, followed by V0/V0′ subsequence, and followed by V1/V1′ subsequence. Letting Noutput1=Npayload/R denote the length of the output sequence, for the modulation coding schemes listed in Table 1, R=1/5, Npayload=3042 or 2048 for Rate 1 and 2, respectively.
Sequence reorganization and symbol reordering is summarized, in Table 2:
After re-ordering of the symbols, subblock repetition is performed, as next explained.
In step 601, if Ntotal is larger than Noutput1 the output sequence Soutput1 is expanded, in which the subsequence U is added at the end of Soutput1, and Noutput1=Noutput1+Npayload (step 603). In step 605, the process again determines whether Ntotal>Noutput1, if true, the subsequence V0/V0′ is added at the end of Soutput1, and Noutput1=Noutput1+Npayload×2 as in step 607.
Next, in step 609, if Ntotal>Noutput1′, the subsequence V1/V1′ is added at the end of Soutput1, and Noutput1=Noutput1+Npayload×2, as in step 611. The steps 601 through 611 are repeated to form a new Soutput1 until Ntotal≦Noutput1.
It is noted that for the MCS in Table 1, subblock repetition is performed for the case of 2048 payload transmitted in 3-slot duration—shown in
After this subblock repetition stage, Ntotal≦Noutput1, Noutput1 is equal to 5 Npayload, or 6 Npayload (for the case of 2 k, 3 slots). It is noted that Ntotal=3840×n, for n=1, 2, or 3 slots.
In step 701, initialization of Nsubseq=0 and Noutput2=0 is performed. Next, in step 703, the process determines whether Noutput2<Ntotal. If Noutput2<Ntotal, then Noutput2 and Nsubseq can be updated as follows. If Nsubseq mod 3 is equal to 0 (step 705), Noutput2=Noutput2+Npayload (step 707), otherwise, Noutput2=Noutput2+Npayload×2 (step 709). In step 711, the process sets Nsubseq=Nsubseq+1. Steps 705-711 are repeated until Noutput2≧Ntotal.
A puncture of the (Nsubseq−1)-th subsequence is shown in
As an example, for a 3 k payload and 3 slots, Noutput1=5*3072=15360. Soutput1 includes U subsequence, followed by V0/V0′ subsequence, and followed by V1/V1′ subsequence. Ntotal=3840*3=11520, Nsubseq=3, Noutput2=15360. Soutput2 includes U subsequence, followed by V0/V0′ subsequence, and followed by 2304 parity bits uniformly punctured over V1/V1′ subsequence.
As seen in the figure, the Ntotal symbols of sequence Soutput2 as in step 1101, are written into a 3-dimensional cubical array with R rows, C≡2m columns, and L levels. Symbols are written into the 3-dimensional array with level-index incrementing first, followed by column-index, followed by row-index. Next, the array is shifted, per step 1103. That is, the linear array of R symbols, at the c-th column and l-th level, is end-around-shifted by (c×L+l)mod R.
Next, the linear array of C symbols, at each given level and row, is bit-reverse interleaved (e.g., based on column index), per step 1105. Thereafter, level-interleaving is performed, as in step 1107. According to one embodiment, the linear array of L symbols, at each given row and column, is level-interleaved (based on level index) as follows. The L symbols are written into a 2-dimensional level-matrix with p rows and q columns. The symbols are written into the level-matrix with row-index incrementing first, followed by column-index. Additionally, the symbols from the level-matrix is read out with column-index incrementing first, followed by row-index. In step 1109, the symbols from the cubical array is read out with row-index incrementing first, followed by column-index, followed by level-index.
It is noted the matrix interleaver parameters depend on the number of transmission slots n, and are shown in Table 4 below.
Let M denote the number of code symbols that can be transmitted in one slot (M=3840 for 320 tone format, M=5184 for 360 tone format). In the case of the 320 tone format (M=3840) with RS3 (5 k payload), the first 2M symbols are subjected to matrix interleaving with R=4 rows, C=128 columns and L=15 levels as specified in Table 5. The next M symbols are subjected to matrix interleaving with R=4 rows, C=64 columns and L=15 levels.
For RS1, the next M symbols are subjected to matrix interleaving with R=4 rows, C=64 columns and L=15 levels as specified below. For RS2, the next (5N−2M=2560) symbols are subjected to matrix interleaving with R=4 rows, C=128 columns and L=5 levels as specified in C.S00024-A.
In the case of 360 tone format (M=5184), the first M symbols are subjected to matrix interleaving with R=4 rows, C=16 columns and L=81 levels (per Table 5). The next M symbols are subjected to matrix interleaving with R=4 rows, C=16 columns and L=81 levels. For RS4, the next (3N−2M=1920) symbols are subjected to matrix interleaving with R=4 rows, C=32 columns and L=15 levels. For RS5, the next (5N−2M=4992) symbols are subjected to matrix interleaving with R=4 rows, C=32 columns and L=39 levels.
In an alternative embodiment, the channel interleaving scheme follows that described in the Appendix.
One of ordinary skill in the art would recognize that the processes for supporting channel interleaving and signal transmission may be implemented via software, hardware (e.g., general processor, Digital Signal Processing (DSP) chip, an Application Specific Integrated Circuit (ASIC), Field Programmable Gate Arrays (FPGAs), etc.), firmware, or a combination thereof. Such exemplary hardware for performing the described functions is detailed below with respect to
The computing system 1300 may be coupled via the bus 1301 to a display 1311, such as a liquid crystal display, or active matrix display, for displaying information to a user. An input device 1313, such as a keyboard including alphanumeric and other keys, may be coupled to the bus 1301 for communicating information and command selections to the processor 1303. The input device 1313 can include a cursor control, such as a mouse, a trackball, or cursor direction keys, for communicating direction information and command selections to the processor 1303 and for controlling cursor movement on the display 1311.
According to various embodiments of the invention, the processes described herein can be provided by the computing system 1300 in response to the processor 1303 executing an arrangement of instructions contained in main memory 1305. Such instructions can be read into main memory 1305 from another computer-readable medium, such as the storage device 1309. Execution of the arrangement of instructions contained in main memory 1305 causes the processor 1303 to perform the process steps described herein. One or more processors in a multi-processing arrangement may also be employed to execute the instructions contained in main memory 1305. In alternative embodiments, hard-wired circuitry may be used in place of or in combination with software instructions to implement the embodiment of the invention. In another example, reconfigurable hardware such as Field Programmable Gate Arrays (FPGAs) can be used, in which the functionality and connection topology of its logic gates are customizable at run-time, typically by programming memory look up tables. Thus, embodiments of the invention are not limited to any specific combination of hardware circuitry and software.
The computing system 1300 also includes at least one communication interface 1315 coupled to bus 1301. The communication interface 1315 provides a two-way data communication coupling to a network link (not shown). The communication interface 1315 sends and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information. Further, the communication interface 1315 can include peripheral interface devices, such as a Universal Serial Bus (USB) interface, a PCMCIA (Personal Computer Memory Card International Association) interface, etc.
The processor 1303 may execute the transmitted code while being received and/or store the code in the storage device 1309, or other non-volatile storage for later execution. In this manner, the computing system 1300 may obtain application code in the form of a carrier wave.
The term “computer-readable medium” as used herein refers to any medium that participates in providing instructions to the processor 1303 for execution. Such a medium may take many forms, including but not limited to non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks, such as the storage device 1309. Volatile media include dynamic memory, such as main memory 1305. Transmission media include coaxial cables, copper wire and fiber optics, including the wires that comprise the bus 1301. Transmission media can also take the form of acoustic, optical, or electromagnetic waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include, for example, a floppy disk, a flexible disk, hard disk, magnetic tape, any other magnetic medium, a CD-ROM, CDRW, DVD, any other optical medium, punch cards, paper tape, optical mark sheets, any other physical medium with patterns of holes or other optically recognizable indicia, a RAM, a PROM, and EPROM, a FLASH-EPROM, any other memory chip or cartridge, a carrier wave, or any other medium from which a computer can read.
Various forms of computer-readable media may be involved in providing instructions to a processor for execution. For example, the instructions for carrying out at least part of the invention may initially be borne on a magnetic disk of a remote computer. In such a scenario, the remote computer loads the instructions into main memory and sends the instructions over a telephone line using a modem. A modem of a local system receives the data on the telephone line and uses an infrared transmitter to convert the data to an infrared signal and transmit the infrared signal to a portable computing device, such as a personal digital assistant (PDA) or a laptop. An infrared detector on the portable computing device receives the information and instructions borne by the infrared signal and places the data on a bus. The bus conveys the data to main memory, from which a processor retrieves and executes the instructions. The instructions received by main memory can optionally be stored on storage device either before or after execution by processor.
A radio network 1400 includes mobile stations 1401 (e.g., handsets, terminals, stations, units, devices, or any type of interface to the user (such as “wearable” circuitry, etc.)) in communication with a Base Station Subsystem (BSS) 1403. According to one embodiment of the invention, the radio network supports Third Generation (3G) services as defined by the International Telecommunications Union (ITU) for International Mobile Telecommunications 2000 (IMT-2000).
In this example, the BSS 1403 includes a Base Transceiver Station (BTS) 1405 and Base Station Controller (BSC) 1407. Although a single BTS is shown, it is recognized that multiple BTSs are typically connected to the BSC through, for example, point-to-point links. Each BSS 1403 is linked to a Packet Data Serving Node (PDSN) 1409 through a transmission control entity, or a Packet Control Function (PCF) 1411. Since the PDSN 1409 serves as a gateway to external networks, e.g., the Internet 1413 or other private consumer networks 1415, the PDSN 1409 can include an Access, Authorization and Accounting system (AAA) 1417 to securely determine the identity and privileges of a user and to track each user's activities. The network 1415 comprises a Network Management System (NMS) 1431 linked to one or more databases 1433 that are accessed through a Home Agent (HA) 1435 secured by a Home AAA 1437.
Although a single BSS 1403 is shown, it is recognized that multiple BSSs 1403 are typically connected to a Mobile Switching Center (MSC) 1419. The MSC 1419 provides connectivity to a circuit-switched telephone network, such as the Public Switched Telephone Network (PSTN) 1421. Similarly, it is also recognized that the MSC 1419 may be connected to other MSCs 1419 on the same network 1400 and/or to other radio networks. The MSC 1419 is generally collocated with a Visitor Location Register (VLR) 1423 database that holds temporary information about active subscribers to that MSC 1419. The data within the VLR 1423 database is to a large extent a copy of the Home Location Register (HLR) 1425 database, which stores detailed subscriber service subscription information. In some implementations, the HLR 1425 and VLR 1423 are the same physical database; however, the HLR 1425 can be located at a remote location accessed through, for example, a Signaling System Number 7 (SS7) network. An Authentication Center (AuC) 1427 containing subscriber-specific authentication data, such as a secret authentication key, is associated with the HLR 1425 for authenticating users. Furthermore, the MSC 1419 is connected to a Short Message Service Center (SMSC) 1429 that stores and forwards short messages to and from the radio network 1400.
During typical operation of the cellular telephone system, BTSs 1405 receive and demodulate sets of reverse-link signals from sets of mobile units 1401 conducting telephone calls or other communications. Each reverse-link signal received by a given BTS 1405 is processed within that station. The resulting data is forwarded to the BSC 1407. The BSC 1407 provides call resource allocation and mobility management functionality including the orchestration of soft handoffs between BTSs 1405. The BSC 1407 also routes the received data to the MSC 1419, which in turn provides additional routing and/or switching for interface with the PSTN 1421. The MSC 1419 is also responsible for call setup, call termination, management of inter-MSC handover and supplementary services, and collecting, charging and accounting information. Similarly, the radio network 1400 sends forward-link messages. The PSTN 1421 interfaces with the MSC 1419. The MSC 1419 additionally interfaces with the BSC 1407, which in turn communicates with the BTSs 1405, which modulate and transmit sets of forward-link signals to the sets of mobile units 1401.
As shown in
The PCU 1436 is a logical network element responsible for GPRS-related functions such as air interface access control, packet scheduling on the air interface, and packet assembly and re-assembly. Generally the PCU 1436 is physically integrated with the BSC 1445; however, it can be collocated with a BTS 1447 or a SGSN 1432. The SGSN 1432 provides equivalent functions as the MSC 1449 including mobility management, security, and access control functions but in the packet-switched domain. Furthermore, the SGSN 1432 has connectivity with the PCU 1436 through, for example, a Frame Relay-based interface using the BSS GPRS protocol (BSSGP). Although only one SGSN is shown, it is recognized that that multiple SGSNs 1431 can be employed and can divide the service area into corresponding routing areas (RAs). A SGSN/SGSN interface allows packet tunneling from old SGSNs to new SGSNs when an RA update takes place during an ongoing Personal Development Planning (PDP) context. While a given SGSN may serve multiple BSCs 1445, any given BSC 1445 generally interfaces with one SGSN 1432. Also, the SGSN 1432 is optionally connected with the HLR 1451 through an SS7-based interface using GPRS enhanced Mobile Application Part (MAP) or with the MSC 1449 through an SS7-based interface using Signaling Connection Control Part (SCCP). The SGSN/HLR interface allows the SGSN 1432 to provide location updates to the HLR 1451 and to retrieve GPRS-related subscription information within the SGSN service area. The SGSN/MSC interface enables coordination between circuit-switched services and packet data services such as paging a subscriber for a voice call. Finally, the SGSN 1432 interfaces with a SMSC 1453 to enable short messaging functionality over the network 1450.
The GGSN 1434 is the gateway to external packet data networks, such as the Internet 1413 or other private customer networks 1455. The network 1455 comprises a Network Management System (NMS) 1457 linked to one or more databases 1459 accessed through a PDSN 1461. The GGSN 1434 assigns Internet Protocol (IP) addresses and can also authenticate users acting as a Remote Authentication Dial-In User Service host. Firewalls located at the GGSN 1434 also perform a firewall function to restrict unauthorized traffic. Although only one GGSN 1434 is shown, it is recognized that a given SGSN 1432 may interface with one or more GGSNs 1433 to allow user data to be tunneled between the two entities as well as to and from the network 1450. When external data networks initialize sessions over the GPRS network 1450, the GGSN 1434 queries the HLR 1451 for the SGSN 1432 currently serving a MS 1441.
The BTS 1447 and BSC 1445 manage the radio interface, including controlling which Mobile Station (MS) 1441 has access to the radio channel at what time. These elements essentially relay messages between the MS 1441 and SGSN 1432. The SGSN 1432 manages communications with an MS 1441, sending and receiving data and keeping track of its location. The SGSN 1432 also registers the MS 1441, authenticates the MS 1441, and encrypts data sent to the MS 1441.
A radio section 1515 amplifies power and converts frequency in order to communicate with a base station, which is included in a mobile communication system (e.g., systems of
In use, a user of mobile station 1501 speaks into the microphone 1511 and his or her voice along with any detected background noise is converted into an analog voltage. The analog voltage is then converted into a digital signal through the Analog to Digital Converter (ADC) 1523. The control unit 1503 routes the digital signal into the DSP 1505 for processing therein, such as speech encoding, channel encoding, encrypting, and interleaving. In the exemplary embodiment, the processed voice signals are encoded, by units not separately shown, using the cellular transmission protocol of Code Division Multiple Access (CDMA), as described in detail in the Telecommunication Industry Association's TIA/EIA/IS-95-A Mobile Station-Base Station Compatibility Standard for Dual-Mode Wideband Spread Spectrum Cellular System; which is incorporated herein by reference in its entirety.
The encoded signals are then routed to an equalizer 1525 for compensation of any frequency-dependent impairments that occur during transmission though the air such as phase and amplitude distortion. After equalizing the bit stream, the modulator 1527 combines the signal with a RF signal generated in the RF interface 1529. The modulator 1527 generates a sine wave by way of frequency or phase modulation. In order to prepare the signal for transmission, an up-converter 1531 combines the sine wave output from the modulator 1527 with another sine wave generated by a synthesizer 1533 to achieve the desired frequency of transmission. The signal is then sent through a PA 1519 to increase the signal to an appropriate power level. In practical systems, the PA 1519 acts as a variable gain amplifier whose gain is controlled by the DSP 1505 from information received from a network base station. The signal is then filtered within the duplexer 1521 and optionally sent to an antenna coupler 1535 to match impedances to provide maximum power transfer. Finally, the signal is transmitted via antenna 1517 to a local base station. An automatic gain control (AGC) can be supplied to control the gain of the final stages of the receiver. The signals may be forwarded from there to a remote telephone which may be another cellular telephone, other mobile phone or a land-line connected to a Public Switched Telephone Network (PSTN), or other telephony networks.
Voice signals transmitted to the mobile station 1501 are received via antenna 1517 and immediately amplified by a low noise amplifier (LNA) 1537. A down-converter 1539 lowers the carrier frequency while the demodulator 1541 strips away the RF leaving only a digital bit stream. The signal then goes through the equalizer 1525 and is processed by the DSP 1005. A Digital to Analog Converter (DAC) 1543 converts the signal and the resulting output is transmitted to the user through the speaker 1545, all under control of a Main Control Unit (MCU) 1503—which can be implemented as a Central Processing Unit (CPU) (not shown).
The MCU 1503 receives various signals including input signals from the keyboard 1547. The MCU 1503 delivers a display command and a switch command to the display 1507 and to the speech output switching controller, respectively. Further, the MCU 1503 exchanges information with the DSP 1505 and can access an optionally incorporated SIM card 1549 and a memory 1551. In addition, the MCU 1503 executes various control functions required of the station. The DSP 1505 may, depending upon the implementation, perform any of a variety of conventional digital processing functions on the voice signals. Additionally, DSP 1505 determines the background noise level of the local environment from the signals detected by microphone 1511 and sets the gain of microphone 1511 to a level selected to compensate for the natural tendency of the user of the mobile station 1501.
The CODEC 1513 includes the ADC 1523 and DAC 1543. The memory 1551 stores various data including call incoming tone data and is capable of storing other data including music data received via, e.g., the global Internet. The software module could reside in RAM memory, flash memory, registers, or any other form of writable storage medium known in the art. The memory device 1551 may be, but not limited to, a single memory, CD, DVD, ROM, RAM, EEPROM, optical storage, or any other non-volatile storage medium capable of storing digital data.
An optionally incorporated SIM card 1549 carries, for instance, important information, such as the cellular phone number, the carrier supplying service, subscription details, and security information. The SIM card 1549 serves primarily to identify the mobile station 1501 on a radio network. The card 1549 also contains a memory for storing a personal telephone number registry, text messages, and user specific mobile station settings.
While the invention has been described in connection with a number of embodiments and implementations, the invention is not so limited but covers various obvious modifications and equivalent arrangements, which fall within the purview of the appended claims. Although features of the invention are expressed in certain combinations among the claims, it is contemplated that these features can be arranged in any combination and order.
The sequence of Nenc binary symbols at the output of the scrambler is interleaved with a Channel Interleaver. Channel interleaving includes a Symbol Reordering stage followed by a Matrix Interleaving stage. The packet length, Ndata (including data and tail bits) is expressed as Ndata=R×C, where R and C are positive integers. The channel interleaver is described in terms of the parameters R, C, D, M1, M2, M3, L1, L2, and L3 which depend on the rate set corresponding to the broadcast packet and are given in Table 7 for Fixed Mode and in Table 8 for Variable Mode.
The scrambled turbo encoder data and tail output symbols generated with the rate-1/5 encoder (corresponding to Rate Sets 1, 2, and 5) is reordered according to the following procedure:
1. All of the scrambled data and tail turbo encoder output symbols is demultiplexed into five sequences denoted U, V0, V1, V′0, and V′1. The scrambled encoder output symbols is sequentially distributed from the U sequence to the V′1 sequence with the first scrambled encoder output symbol going to the U sequence, the second to the V0 sequence, the third to the V1 sequence, the fourth to the V′0 sequence, the fifth to the V′1 sequence, the sixth to the U sequence, etc.
2. The U, V0, V1, V′0, and V′1 sequences is ordered according to UV0V′0V1V′1. That is, the U sequence of symbols is first and the V′1 sequence of symbols is last.
The scrambled turbo encoder data and tail output symbols generated with the rate-1/3 encoder (corresponding to Rate Sets 3, 4, and 6) is reordered according to the following procedure:
1. All of the scrambled data and tail turbo encoder output symbols is demultiplexed into three sequences denoted U, V0, and V′0. The scrambled encoder output symbols is sequentially distributed from the U sequence to the V′0 sequence with the first scrambled encoder output symbol going to the U sequence, the second to the V0 sequence, the third to the V′0 sequence, the fourth to the U sequence, etc.
2. The U, V0, and V′0 sequences is ordered according to UV0V′0. That is, the U sequence of symbols is first and the V′0 sequence of symbols is last.
The matrix interleaving operation is carried out in the following steps:
1. The Ndata symbols of the U sequence are written into a 2-dimensional rectangular array W with R rows and C columns, where Ndata=R×C. Symbols are written into the 2-dimensional array with column-index incrementing first, followed by the row-index. In other words, the ith incoming symbol, where 0≦i<Ndata goes into the rth row and cth column, where r=[i/C] and c=i mod C and the ranges of r and c indices are given by 0≦r<R and 0≦c<C.
2. The linear array of R symbols, at the cth column of the rectangular array W is end-around shifted by c mod R. In other words, W[r][c] is moved to W[(r+c)modR][c] for all 0≦r<R and 0≦c<C.
3. The Ndata symbols of the V0 sequence, followed by the Ndata symbols of the V′0 sequence are written into a 2-dimensional rectangular array W0 with R rows and 2C columns. Symbols are written into the 2-dimensional array with column-index incrementing first, followed by the row-index. In other words, the ith incoming symbol, where 0≦i<2Ndata goes into the rth row and cth column, where r=[i/2C] and c=i mod 2C and the ranges of r and c indices are given by 0≦r<R and 0≦c<2C.
4. The linear array of R symbols, at the cth column of the rectangular array W0 is end-around shifted by [c/D] mod R. In other words, W0[r][c] is moved to W0[(r+[c/D]) mod R][c] for all 0≦r<R and 0≦c<2C.
5. The two dimensional array W0 is transformed to the two dimensional array W0[ ][σ0] (in other words, the linear array of 2C symbols at each row of the rectangular array W0 is interleaved based on column-index c by moving column σ0[c] of the rectangular array W0 to column c for all 0≦c<2C), where the vector σ0 can be obtained by the following procedure: Let S1, S2, and S3 be ordered sets of integers defined as follows (note that the sets S1, S2, S3 defined by the following procedure partition the set of integers {i|0≦i<2C}):
S
1
={[C/M
1
]+[i*(2C/M1)+0.5]|0≦i<M1}
S
2
={[C/M
2
]+[i*(2C/M2)+0.5]|0≦i<M2}−S1
S
3
={i|0≦i<2C}−S1−S2.
The elements of the vector σ0 [c] as c ranges from 0 to 2C−1 are obtained by first taking all the elements of the ordered set S1 (that is the first M1 elements of the linear array σ0 come from the ordered set S1), and then all the elements of S2, and finally all the elements of S3 in the order the elements appear in the respective ordered sets.
6. If the encoder is of rate-1/5, then a 2-dimensional rectangular array W1 with R rows and 2C columns is constructed by following the same procedure described in Step 3 by replacing all occurrences of the rectangular array W0 and the sequences V0 and V′0 by the rectangular array W1 and the sequences V1 and V′1, respectively. If the encoder is of rate-1/3, then Steps 7 and 8 below are skipped.
7. Each column of the rectangular array W1 is end-around shifted by applying the procedure described in Step 4 with the array W0 replaced by the array W1.
8. The two dimensional array W1 is transformed to the two dimensional array W1[ ][σ1] (in other words, the linear array of 2C symbols at each row of the rectangular array W1 is interleaved based on column-index c by moving column ([c] of the rectangular array W1 to column c for all 0≦c<2C), where the vector σ1 can be obtained by the following procedure: Let S4 and S5 be ordered sets of integers defined as follows (note that the sets S4 and S5 defined by the following procedure partition the set of integers {i|0≦i<2C}):
S
4
={[C/M
3
]+[i*(2C/M3)+0.5]|0≦i<M3}
S
5
={i|0≦i<2C}−S4.
The elements of the vector σ1[c] as c ranges from 0 to 2C−1 are obtained by first taking all the elements of the ordered set S4 (that is, the first M3 elements of the linear array a come from S4), and then all the elements of S5 in the order the elements appear in the respective ordered sets.
9. If the encoder is of rate-1/5, then a rectangular array Z of R rows and 5C columns will be formed by juxtaposing the rectangular arrays W, W0, and W1, in that order, that is, Z=[W W0 W1]. If the encoder is of rate-1/3, then a rectangular array Z of R rows and 3C columns will be formed by juxtaposing the rectangular arrays W and W0, in that order, that is, Z=[W W0].
10. The columns of the rectangular array Z are interleaved by the column index c by the following procedure: For columns 0≦c<L1, each column c is moved to column (79 c) mod L1. For columns L1≦c<L1+L2, each column c is moved to column L1+(79(c−L1)) mod L2. For columns L1+L2≦c<L1+L2+L3, each column c is moved to column L1+L2+(79(c−L1−L2)) mod L3. The remaining columns of the rectangular array Z, if any, are not interleaved.
11. The Nenc symbols of the rectangular array Z are read out with row-index incrementing first, followed by the column-index. In other words, the ith output symbol, where 0≦i<Nenc, comes from the rth row and cth column of the rectangular array Z where c=[i/R] and r=i mod R and the ranges of r and c indices are given by 0≦r<R and 0≦c<C′ where the number of columns C′ of the rectangular array Z is given by C′=5C if the encoder is of rate-1/5 and C′=3C if the encoder is of rate-1/3. Note also that Nenc=R×C′.
This application claims the benefit of the earlier filing date under 35 U.S.C. §119(e) of U.S. Provisional Application Ser. No. 60/680,285 filed May 12, 2005, entitled “Enhanced Channel Interleaver For Supporting Communication Services,” and U.S. Provisional Application Ser. No. 60/677,495 filed May 4, 2005, entitled “Method and Apparatus for Code Puncturing and Channel Interleaving”; the entireties of which are incorporated by reference.
Number | Date | Country | |
---|---|---|---|
60680285 | May 2005 | US | |
60677495 | May 2005 | US |