Patent Application
20080052336
The invention will now be described in greater detail based on various embodiments with reference to the accompanying drawings, in which:
In the following, the invention, according to certain embodiments, will be described in connection with an exemplary OFDM transmission system.
A computationally demanding operation in an OFDM transmitter, receiver or transceiver is the FFT or IFFT calculation, respectively. When designing an FFT, area is traded against speed. An efficient option to implement an FFT is to use a timeshared butterfly (where the term “butterfly” indicates the shape of the processing stage) and a memory. However, this approach involves the draw-backs of large latency and low throughput. Latency is critical if the system is designed for real-time applications, which is to be expected in OFDM systems. To decrease latency and increase throughput, a pipelined FFT architecture can be used. A drawback thereof is that the required amount of hardware is increased, mostly due to extra multipliers.
In connection with FFT or IFFT processing, bit reversed sequences are processed or generated. The term “bit reversed” is used to indicate that the addresses needed to access the sequence in correct order are the normal binary addresses read backwards, i.e., right to left. For example, this means that the binary address “110” (which corresponds to the decimal address “6”) becomes the binary address “011” (which corresponds the decimal address “3”). The above mentioned pipelined FFTs have the property that the output sequence is bit reversed compared to the input sequence. Depending on the architecture, a pipelined FFT will either produce the output sequence in bit reversed order or use the input sequence in bit reversed order.
A pipelined FFT can be implemented either as a decimation in time (DIT) or as a decimation in frequency (DIF). The difference is whether the multiplication is performed first (DIT) or last (DIF) in the butterfly. No matter whether a DIT or DIF approach is used for the FFT, the sequence should be transmitted in the correct order over the channel, i.e. the IFFT output should be transmitted in correct order. One method to solve the bit reversing in pipelined FFTs is to add a buffer before or after the FFT processor that can reorder the Sequence. However, as indicated in the introductory part, this will increase both hardware and delay.
The OFDM system is implemented using a combination of an FFT stage 26 in the receiver 20 and a mathematically equivalent IFFT stage 16 in the transmitter 10. The OFDM system treats the source symbols at the input of the transmitter 10 as though they are in the frequency domain. These symbols are processed in some preceding stages, including a combined interleaving and bit reordering stage 12 and other operations 14 and are then used as inputs to the IFFT stage 16 which transforms the signal into the time domain. To achieve this, the IFFT stage 16 processes N symbols at a time, where N is the number of subcarriers in the OFDM system. Each of the N input symbols has a symbol period of T seconds. Each input symbol acts like a complex weight for a corresponding sinusoidal basis function. Since the input symbols are complex, their values determine both amplitude and phase of the sinusoid for that subcarrier. The IFFT output corresponds to the sum of all N sinusoids. Thus, the IFFT stage 16 provides a simple way to modulate data onto N orthogonal subcarriers. The block of N output samples of the IFFT stage 16 makes up a single OFDM symbol. The length of the OFDM symbol is N·T.
After some additional processing, the time-domain signal output from the IFFT stage 16 is transmitted across a transmission channel to the receiver 20. At the receiver 20, the FFT stage 26 is used to process the received signal in an inverse manner after some initial processing stages, to bring it back into the frequency domain. The converted or transformed signal is subjected to some further processing including a combined de-interleaving and bit reordering stage 22 and other preceding operations 24 to obtain the original source symbols.
The present OFDM system according to one embodiment of the invention comprises frequency-domain interleaving, which means that the data is interleaved in the combined interleaving and bit reordering stage 12 of the transmitter 10 before it is transferred to the time domain by the IFFT stage 16. In the receiver 20, the data is transferred from time to frequency domain by the FFT stage 26 before it is de-interleaved in the combined de-interleaving and bit reordering stage 22. De-interleaving is required to reverse the interleaving applied in the transmitter 10.
The Cooley-Tukey algorithm is disclosed in James W. Cooley and John W. Tukey, “An algorithm for the machine calculation of complex Fourier series,” Math. Comput. 19, 297-301 (1965). This is a divide and conquer algorithm that recursively breaks down a digital Fourier transformation (DFT) of any composite size N=N1N2 into many smaller DFTs of sizes N1 and N2, along with O(n) multiplications by complex roots of unity traditionally called twiddle factors. If N1 is the radix, it is called a DIT algorithm, whereas if N2 is the radix, it is called a DIF algorithm. One example of use of the Cooley-Tukey algorithm is to divide the transform into two pieces of size n/2 at each step, and is therefore limited to power-of-two sizes, but any factorization can be used in general. These are called the radix-2 and mixed-radix cases, respectively (and other variants have their own names as well).
According to one embodiment, the idea is to use a fast radix-2 single path delay feedback in the IFFT/FFT stages 16, 26 and combine a non-reordered and thus bit-reversed output of the FFT stage 26 with the de-interleaving scheme in the combined de-interleaving and reordering stage 22 of the receiver 20. Additionally, a non-reordered and thus bit-reversed input of the IFFT stage 16 of the transmitter 10 is combined with interleaving scheme of the combined interleaving and bit reordering stage 12. This means, no reordering is performed in the IFFT and FFT stages 16, 26, but this processing is shifted to and combined with the processing at the correspondingly modified interleaver/de-interleaver functionality of the combined interleaving and bit reordering stage 12 and the combined de-interleaving and bit reordering stage 22, respectively. Through this measure, the delay of the two IFFT and IFFT stages 16, 26 in the receiver 10 and transmitter 20, respectively, can be reduced to two OFDM symbols and also memory requirements are minimized.
The same applies to the similar processing at the IFFT stage 16 on the transmitter side, where the required reordering is covered by the modified interleaving processing at the combined interleaving and bit reordering stage 12, so that no additional memory space and processing stage is required at the IFFT stage 16.
It is apparent that this advantage is not restricted to the specific radix-2 processing shown in
Of course, other address modifications may be introduced depending on the required reordering processing. Moreover, the functionality of the reordering unit 34 may be incorporated into the address generator 32.
Additionally, it is noted that the functionalities described in connection with
According to
According to
The approach described above leads to a shorter computation time and reduced memory requirements for the combined FFT and de-interleaving operation at the receiver 20. The same applies to the combined interleaving and IFFT operation at the transmitter 10.
Moreover, as it is also possible to use the FFT with a bit-reversed input and the IFFT with a bit-reversed output, the proposed scheme can also be used for systems with time-domain interleaving. Of course, a receiver, which is using this scheme, is still able to operate correctly in a system with a transmitter, which does not use this scheme—and vice versa. This also applies to a transmitter following the scheme.
In summary, signal processing methods and apparatuses for reducing latency in fast Fourier transformation (FFT) related systems have been described. In a first processing direction, an interleaving processing is performed to obtain an interleaved data sequence which is then subjected to an IFFT processing, wherein the interleaving processing comprises a bit re-ordering processing of the IFFT processing. In an opposite second processing direction, an FFT processing is performed with a bit-reversed output data sequence which is then subjected to a de-interleaving processing, wherein the de-interleaving processing comprises a bit re-ordering processing required for reordering said bit-reversed output data sequence. Due to the fact that the reordering processing is incorporated into the interleaving/de-interleaving processing, latency can be reduced and memory space can be saved.
The preferred embodiments can be used in any FFT-related processing environment, for example in wireless access networks, such an WLAN or WIMAX networks, or alternatively in any other signal processing environment which provides a combination of interleaving or de-interleaving processing and FFT or IFFT processing. The preferred embodiments may thus vary within the scope of the attached claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 06 017 463.8 | Aug 2006 | EP | regional |
