Patent Application
20060239393
1. Field of the Invention
The present invention relates to communication systems and, more particularly, to circuitry for providing accurate, synchronized timing between a transmitter and receiver of multimedia content.
2. Description of the Related Art
Communication systems that communicate multimedia content, such as audio and video files, are required to utilize accurate timing such that the sequence of events within the multimedia content can be reconstructed at the receiver. To facilitate such timing synchronization certain protocols are applied to the transmission. The source circuitry (the transmitter) utilizes a time stamp flag (TSF) timer and a media access control (MAC) protocol such that a 27 MHz clock can be used in the source circuitry for timing of the transmission without directly encoding the clock into the transmission.
The sink circuitry (the receiver) utilizes the TSF to properly order the multimedia information for display by the receiver. However, the 27 MHz clock that is used in the sink circuitry is not synchronized with the source circuitry 27 MHz clock, i.e., the receiver-transmitter operate as an open-loop system with respect to the 27 MHz clock. As such, any phase shift that occurs between the source and the sink circuitry due to channel dynamics causes a timing error to accumulate between the source and sink circuitry. When the misalignment has a length of approximately a frame of multimedia data, the sink circuitry deletes or drops a frame. In most applications, a single dropped frame to realign the source and sink circuitry is not recognized by a viewer or user of the multimedia data. However, in some situations, a frame drop is recognizable to the viewer and must be avoided.
Therefore, there is a need in the art for circuitry that provides synchronization between the source and sink circuits of a communication system.
The present invention is clock synchronization circuitry for a receiver in a communication system. In the first embodiment of the invention, the time stamp flags, which are generated from source clock in a known fixed period, are transmitted to the receiver. When the time stamp flags are detected at the receiver, the receiver translates the time stamp flags of a known fixed time interval into clock cycles that are compared to the sink local clock signal to generate an error value. The error value is processed in a loop filter and coupled to a first numerically controlled oscillator (NCO) to provide a coarse timing signal. The first NCO, a comparison circuit and loop filter forms a first loop. A second loop controls a second NCO to produce a finely controlled clock signal. In one embodiment of the invention, this circuit is used to maintain source-sink timing synchronization of a 27 MHz clock in a multimedia communications system such that frame drops are reduced.
In a second embodiment of the invention, two distinct frequency control loops are utilized to control two NCOs. The first NCO is controlled by an inner loop for coarse timing control and the second NCO is controlled by an outer loop to provide fine timing control.
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
The sink circuitry 106 includes a sink clock circuit 112 and receiver circuitry 114. The receiver circuitry 114 extracts the time stamps from the received data and provides the time stamps on path 116. The time stamps are used by the sink clock circuit 112 to synchronize the sink clock signal to the source clock circuit 108 in accordance with the present invention. The data is extracted from the received signal using the clock signal.
The output of the NCO 204 is coupled to a clock counter 206 that counts the clock signals in a fixed period within which the coefficients of loop filter 216 are updated, for example, a 10 millisecond period. The output from the clock counter 206 is applied to a clock difference generator 208 that calculates the difference between the current counter value and previous counter value of clock counter 206 every 10 ms. The normal output of block 208 has the value of 270,000 in every 10 ms period (27 MHz×10 ms=270,000 cycles), i.e., without receiving a TSF signal from receiver circuitry 232, the output of the clock difference generator is merely the output of the clock counter every 10 ms. However, while the clock difference generator 208 receives the TSF signal from receiver circuitry 232, the clock difference generator 208 instantly ouputs the clock difference between current value of the clock counter and the previous counter value of the clock counter at 10 ms. The output value may have a value different from 270,000, and this difference value is used to calculate the clock difference between the transmitter's and the receiver's clocks in each 100 ms period. For example, assume the time stamp flags are generated at 100 ms from the source clock, or every 2,700,000 clock cycles. If the receiver's clock has a slightly different frequency, say 2,699,000 Hz, then, every 100 ms interval, the clock difference is (27,000,000−26,990,000)×100 ms=1000 cycles. For this example, the clock difference generator produces a count of 270,000 every 10 ms except at the 100 ms time stamp flag occurrence where the generator would produce a count of 269,000.
The output from the difference generator 208 is coupled to a subtractor 210. The subtractor 210 subtracts an expected value from the value of the difference generator 208. The expected value, when the clocks are running at 27 MHz and a 10 millisecond period is used, is set at 270000 (i.e., 27 MHz×10 ms). For the example above where the receiver clock runs at 26.99 MHz, the output of the subtractor would be zero for most 10 ms intervals and 1000 at each 100 ms interval.
The output of the subtractor 210 (i.e., the clock error) is coupled to a running sum block 212. The running sum block 212 is a data buffer having a length of equal to n. The running sum block 212 sums the last n input data bits. The buffer size is generally set to 256, i.e., 256 data are summed. The output of the running sum block 212 is coupled to a scaler 214 that scales the input signal by a constant factor, e.g., 1/270,000. The scaler 214 is also used to establish the updating constants, Kp and K1 of the loop filter 216 as discussed below. The loop filter 216 is an IIR filter having a transfer function H(z) of:
where Kp and Ki are the gains of the IIR filter. Kp and Ki are used to control the speed of convergence of loop filter 216 and their values depend on the update rate (e.g., 10 ms). Here, Kp=0.0066 and Ki=0.0235 are chosen as exemplary values.
The scaler 222 is designed to scale the output of the loop filter by a constant factor, e.g., 12. The scaler 222 has its output coupled to the NCO 204. The NCO 204 is a numerically controlled clock. In normal use, the NCO always divides the 324 MHz clock by 12 to produce a 27 MHz output. By adding or deleting an extra clock cycle of 324 MHz during some of the 12 cycle periods, the output clock signal of the NCO 204 can be coarsely synchronized to the 27 MHz clock of the source. The NCO 204 forms a phase offset accumulator which normalizes its output by using a saw tooth non-lineararity having a range between 0.5 and −0.5. If the accumulator becomes greater than 0.5, then the accumulator will subtract 1 and add one clock cycle of the 324 MHz reference. Oppositely, if the accumulator becomes less than −0.5, the accumulator adds 1.0 and deletes one clock cycle of the 324 MHz reference to its output. The NCO 204, counter 206, difference generator 208, subtractor 210, running sum block 212, scalers 214 and 222 and the loop filter 216 form a first loop 250 of the dual loop DPLL. The first loop 250 performs coarse timing synchronization. A second loop 252 includes the components of the first loop plus a frequency offset compensator 218, scaler 220, subtractor 224, and NCO 202. The second loop 252 provides fine tuning of the NCO 202.
The frequency offset compensator 218 is coupled to the loop filter 216 and is used as part of the second loop 252 to tune the NCO 202. The frequency offset compensator 218 monitors a frequency offset produced by the loop filter 216. The compensator 218 uses a table mapping or a simple function to process the frequency offset and determine how much frequency offset is needed to be compensated to accurately tune the NCO 202. For example, if the frequency offset measured in parts per million (ppm) is equal to 33, then the system needs to add about 24 Hz to the output of the NCO 202. The scaling block 220 adds a constant to the frequency offset compensator output. An addition generator 224 adds the frequency offset compensator output from output of scaler 222. The sum signal created by the adder 224 is applied to the NCO 202 to adjust its frequency in a fine manner to obtain an accurate 27 MHz clock that is synchronized to the time stamps produced by the source circuitry.
In this manner, the sink clock is essentially synchronized to the source clock using a dual loop, DPLL and thus will avoid the need to drop frames to maintain synchronization.
The time stamp flag (TSF) is chosen for 27 MHz clock synchronization between the source side and the sink side. The main reason is that the TSF timer is a most reliable clock timer and creates a relatively low amount of phase jitter. The fixed time interval of the TSF needs to be selected to be a value that enables accurate synchronization without using an undue amount of processing power. For example, if the fixed time interval is short (e.g., less than 10 ms), then the synchronization time for the sink clock will be fast as well as being very accurate. However, because more TSFs will be transmitted through the channel, the use of a short fixed interval decreases the data throughput and increases the processing power required to process the rapidly arriving TSFs. If the fixed time interval is long, (i.e., more than one second), then the synchronization time for the sink clock will be slow as well as less accurate. However, because less TSFs are being transmitted, the use of a long time interval increases the data throughput and reduces the processing power of the system. A fixed time interval of about 100 ms provides relatively rapid and accurate sink clock synchronization as well as sufficient data throughput and limited power use. Additionally, a 100 ms TSF interval is evenly divisible by the 5 or 10 ms update rate used in the sink clock circuitry. By using a dual loop design with two numerically controlled oscillators to provide coarse and fine timing control, the present invention provides a very accurate clock that is synchronized to the source clock signal.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
