Patent Application
20080031033
Regardless of the number of match line levels, the match line coupling circuitry 16 comprises match line restoration circuitry 18 and match line decoupling circuitry 20. For ease of explanation only, the match line coupling circuitry 16 is next described with reference to coupling LMLs to GMLs. However, those skilled in the art will readily recognize that the coupling circuitry 16 described herein may couple any hierarchically lower level of match lines to a higher level match line.
With this in mind, the match line restoration circuitry 18 determines whether particular LMLs are to be restored to a pre-evaluation state after a CAM search operation. That is, not all LMLs may be of interest during a particular CAM search operation. For example, the content one or more CAM entries (not shown) or portions of CAM entries may be marked as invalid or masked during evaluation. LMLs corresponding to these entries or partial entries are not of interest. Search results provided by LMLs not of interest are conventionally ignored or discarded during a CAM search operation. Enable information, e.g., one or more valid or masking bits associated with each CAM entry is provided to the match line restoration circuitry 18 for indicating which LMLs are not of interest. In one embodiment, the enable information directly indicates which match lines are not of interest. In another embodiment, the enable information indirectly indicates which match lines are not of interest, e.g., by identifying match lines of interest. Regardless, the match line restoration circuitry 18 uses the enable information to identify the match lines that will be ignored during a CAM search operation.
If a particular match line restoration circuit 18 determines that its corresponding LMLs are not of interest, it prevents those LMLs from being restored to a pre-evaluation state, essentially disabling the LMLs. In one embodiment, the match line restoration circuit 18 prevents the LMLs from being pre-charged. In another embodiment, the match line restoration circuit 18 prevents the LMLs from being pre-discharged. Because the search results associated with these LMLs are not of interest, preventing their restoration to a pre-evaluation state reduces power consumption without adversely affecting operation of the CAM circuit 10. The enable information used by the match line restoration circuitry 18 may be stored within the CAM circuit 10, e.g., as one or more valid bits included in each entry in the CAM circuit 10, or may be provided to the CAM circuit 10.
The enable information is also used by the match line decoupling circuitry 20. The match line decoupling circuitry 20 uses the enable information to prevent LMLs not of interest from affecting their corresponding GMLs. Decoupling an LML not of interest from its GML ensures that the LML will not affect the state of its GML. Instead, only enabled LMLs coupled to the GML may affect the state of the GML, e.g., by discharging it. This prevents unstable CAM circuit 10 behavior while reducing power consumption.
In one embodiment, the match line decoupling circuitry 20 prevents a group of LMLs that have been disabled by the match line restoration circuitry 18 from affecting the state of the GML to which they are coupled. If the enable information indicates that a group of LMLs associated with a particular GML are to be ignored during a CAM search operation, then the match line decoupling circuitry 20 decouples the group of LMLs from that GML. As such, the match line decoupling circuitry 20 prevents individual groups of LMLs from affecting the state of corresponding GMLs when the LMLs are not of interest.
The following is a non-limiting example based on the CAM circuit 10 shown in
The enable signal indicates whether the LML is of interest or not. When the enable signal is a logic one, it causes pre-charging of the LML to be disabled and causes the LML to be decoupled from its GML. Particularly, if the enable signal indicates that the search results associated with the LML are of interest, the match line restoration circuit 18 is activated (e.g., p-FET transistor T7 is switched on). When activated, the match line restoration circuit 18 enables the LML precharge circuit and the inverter by charging their respective source nodes to a logic one value (Vdd). This enables the LML precharge circuit to pre-charge the LML to a logic one value in response to an active restore signal (RESTORE) during a pre-evaluation period. Unlike some conventional circuit techniques, the match line restoration circuit 18 does not adversely impact performance of the CAM circuit 10 when activated. Particularly, the match line restoration circuit does not add additional capacitance to the output node of the CAM cell (not shown) coupled to the LML when activated. Because the match line restoration circuit 18 is not placed in the active signal path coupling the LML to the output node of the CAM cell, no additional capacitive loading results.
When the LML is of interest, the enable signal also causes the match line decoupling circuit 20 to be deactivated (e.g., n-FET transistor T8 is switched off). When the match line decoupling circuit 20 is deactivated, the state of the GML is affected by the LML. As a result, when the n-FET transistor T6 of the GML evaluation circuit is activated in response to an enabled clock signal (GML_CLK), the state of the LML controls whether the n-FET transistor T5 of the GML evaluation circuit is switched on or off. If the n-FET transistor T5 is switched on, the GML discharges to ground. Conversely, the GML remains unaffected by the LML irrespective of the LML's state when the n-FET transistor T5 is switched off. As a result, the match line decoupling circuit 20 does not affect the GML state when deactivated. Instead, the state of the GML reflects that of only the enabled LMLs.
If the LML is not of interest, the match line restoration circuit 18 is deactivated (e.g., p-FET transistor T7 is switched off). When deactivated, the match line restoration circuit 18 decouples the source nodes of the LML precharge circuit and the inverter from the power source. The LML precharge circuit is unable to pre-charge the LML when the power source is removed from its source node, thus reducing unnecessary power consumption. Further, the LML is disabled when the match line restoration circuit 18 is deactivated.
In addition, the enable signal causes the match line decoupling circuit 20 to be activated when the LML is disabled. The match line decoupling circuit 20 drives the gate input to the n-FET transistor T5 of the GML evaluation circuit to a logic low value (Vss). When the gate input of the n-FET transistor T5 is low, the state of the LML does not affect that of the GML, and thus the LML is decoupled from its GML. Particularly, the n-FET transistor T5 cannot conduct sufficient current when its gate input is low. As such, the GML, which had been pre-charged during a prior non-evaluation period, cannot be discharged by this particular GML evaluation circuit regardless of the LML's state. When activated, the match line decoupling circuit 20 also prevents unpredictable behavior by the CAM circuit 10 by pulling down the gate input of the n-FET transistor T5 of the GML evaluation circuit. If the gate input of the n-FET transistor T5 is not pulled down, the output node of the inverter (lml_sns) could adversely affect the GML state. For example, the output node of the GML's inverter may float or otherwise act unpredictably when the power source has been removed from its source node. The match line decoupling circuit 20 prevents such sporadic behavior from adversely affecting the GML by preventing the LML from affecting the state of the GML when the LML is not of interest.
The match line restoration and decoupling circuitry 18, 20 may be included in or associated with various kinds of memory devices such as caches and buffers.
The caches 38, 40 and 42 have respective Translation Lookaside Buffers (TLBs) 44, 46 and 48 for performing address translation during cache access operations. Each TLB 44, 46 and 48 has one or more instances of the match line restoration and decoupling circuitry 18, 20. Alternatively, a unified TLB (not shown) may perform address translation for the caches 38, 40 and 42. Regardless, the TLBs 44, 46 and 48 are CAM-based in that a virtual address of interest is provided to the TLBs 44, 46 and 48 and the TLBs 44, 46 and 48 yield corresponding hit or miss results in response. In the event of a hit, a physical address is produced corresponding to the virtual address search field. In the event of a miss, a page table transaction occurs.
The TLBs 44, 46 and 48 have entries (not shown) that contain information for use in translating virtual address to physical addresses. In one embodiment, each TLB entry comprises a virtual address field, a corresponding physical address field and a valid bit. If a virtual address search field matches an entry in one of the TLBs 44, 46 and 48, the corresponding physical address field is output. Otherwise, a page table transaction occurs. The valid bit determines whether a particular TLB entry is valid or not. If invalid, the entry contents are ignored or discarded during address translation. Other enable bits such as page-size bits may determine whether corresponding portions of virtual address bits should participate in address translation.
According to this embodiment, the LML is decoupled from its GML when the p-FET 10 of the match line decoupling circuitry 10 drives the input to the GML inverter circuit (p-FET T2 and n-FET T3) to a logic low value (Vss). When the match line decoupling circuit 20 drives the inverter input to a logic low state, the LML is effectively decoupled from its GML. That is, the LML no longer has an affect on the state of the GML since the inverter outputs a logic one irrespective of the LML state. By driving the inverter input to a logic low state, the GML discharges when its clock input signal (GML_CLK) is active. When the GML is discharged, it is interpreted as a mismatch. Thus, this embodiment of the coupling circuitry 16 prevents false hits from being processed when a TLB 44, 46 and 48 entry is invalid. Alternatively, the coupling circuitry 16 embodiment illustrated in
With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.
