This invention relates to integrated circuits (“ICs”). More particularly, this invention relates to multiplexer circuitry in ICs.
Multiplexers are well-known circuits that accept N selector inputs and 2N data inputs, and generate a single data output. Each binary combination of the N selector inputs will select a corresponding data input and transmit its value to the data output. For simplicity of illustration, the discussion herein will focus on multiplexers with a single selector input, two data inputs, and one data output. However, it will be understood that the concepts discussed herein could be generalized to accommodate N selector inputs and 2N data inputs.
Multiplexers are used extensively in ICs, and are especially common in the datapaths of programmable logic devices (“PLDs”). Such datapaths often include “multiplexer cones,” which are composed of a plurality of multiplexers feeding into each other. That is, the output of each multiplexer is coupled to a data input of another multiplexer, with the exception of the final multiplexer in the cone, which typically drives a register or other output circuitry. Because datapaths often consist of multiple bits, PLDs typically include many “multiplexer cone buses,” which are collections of multiplexer cones that are isomorphic to each other and share the same selector inputs. In addition, wherever a pair of data inputs are electrically equivalent in one multiplexer cone, they are also equivalent in the other cones of the same bus, a property that will become significant later herein.
Because of the prevalence of multiplexer circuitry in ICs, and in PLDs in particular, it is highly desirable to find algorithms that can reduce the cost (e.g., area) of multiplexer circuitry. Such reduction can be achieved, for example, during synthesis, where software code that is written in a hardware description language (“HDL”) is converted into a circuit configuration that can be implemented on an IC. Modern synthesis algorithms typically optimize multibit datapaths one bit at a time. As a result, some optimizations that can yield savings if applied across an entire multiplexer cone bus, but not if applied to individual multiplexer cones, are not used.
In view of the foregoing, it would be desirable to provide methods and apparatus that can reduce the cost of multiplexer circuitry. In particular, it would be desirable to provide methods and apparatus that can reduce the cost of multiplexer cone buses.
In accordance with this invention, methods and apparatus are provided for reducing the cost of multiplexer circuitry. In one embodiment of the invention, a multiplexer cone can be restructured. A first multiplexer and one of its data inputs can be eliminated from a first point of the multiplexer cone. A second multiplexer can be added to a second point in the multiplexer cone that is closer to an output of the multiplexer cone than the first point. The data input of the first multiplexer can be received by the second multiplexer. In addition, selection logic that is coupled to the second multiplexer can be added, such that the logical function of the multiplexer cone remains unchanged by the restructuring process.
In another embodiment of the invention, multiplexer circuitry in a multiplexer cone can be factorized. Electrically equivalent data inputs and corresponding multiplexers in the multiplexer cone can be selected and eliminated. A new multiplexer can be added in the multiplexer cone bus, such that the new multiplexer receives at least one of the data inputs. New selection circuitry can be added and coupled to the new multiplexer.
In yet another embodiment of the invention, the cost of multiplexer circuitry can be reduced. A plurality of maximal multiplexer cones can be found in the multiplexer circuitry and merged into at least one maximal multiplexer cone bus. An optimization can be applied to the at least one maximal multiplexer cone bus that reduces the cost of the multiplexer circuitry, even though it would not reduce the cost if applied only to a single maximal multiplexer cone.
The invention therefore advantageously provides methods and apparatus for reducing the cost of multiplexer circuitry. In particular, the methods and apparatus of the invention can be used to reduce the cost of multiplexer cone buses.
The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:
In
Multiplexers 114 receive data inputs B and E, as well as selector input SEL[3]. As described above, each of data inputs B and E preferably includes three distinct data bits, one for each multiplexer 114. In contrast, signal SEL[3] is preferably a single-bit signal that controls all three multiplexers 114, as required by the definition of a multiplexer cone bus. Thus, when SEL[3] carries a logical “0” value, each multiplexer 114 preferably outputs a distinct bit of signal bus B. Similarly, when SEL[3] carries a logical “1” value, each multiplexer 114 preferably outputs a distinct bit of signal bus E.
The output of each multiplexer 114 is coupled to a data input of a multiplexer 112, which also receives a component bit of data input bus D. All three multiplexers 112 are preferably controlled by selector input SEL[1]. Selector input SEL[1] also preferably controls multiplexers 110, whose data inputs are signal buses B and C. It will be noted that data input bus B is preferably received by multiplexers 110 and multiplexers 114. That is, a data input of each multiplexer 110 is electrically equivalent to a data input of each multiplexer 114, a fact that will become significant later herein.
Proceeding further down the cone, the outputs of multiplexers 110 and 112 are received by multiplexers 108, which are controlled by selector input SEL[2]. The outputs of multiplexers 108 are received by multiplexers 102, which generates output signal Z. Multiplexers 108 also receive data inputs A, and are controlled by selector input SEL[0].
The cost of multiplexer cone bus 100 can be reduced in accordance with the invention by restructuring its circuitry appropriately. As noted before, data input bus B is received by both multiplexers 110 and multiplexers 114. This redundancy can be exploited by eliminating multiplexers 114, multiplexers 110, and their connections to data input bus B, and adding new circuitry. As suggested by
In an abstract sense, multiplexers 114 and their respective component data inputs of bus B have been moved to a new point in multiplexer cone bus 100. To account for this change in topology, selection logic 103 is added. Preferably, selection logic 103 includes an AND gate, and receives the logical inverse of selector input SEL[3], as well as non-inverted selector inputs SEL[1] and SEL[2]. The output of selection logic 103 preferably controls and is received by all three multiplexers 104. It will be noted that the logical function of multiplexer cone bus 100 has been unchanged by the illustrated restructuring. For instance, multiplexer cone bus 100 still outputs data input bus B when SEL[0] is a logical “1,” SEL[2] is a logical “1,” SEL[L] is a logical “1,” and SEL[3] is a logical “1.” Further inspection of the circuits illustrated in
Selection logic 105 is added in order to account for this further restructuring of multiplexer cone bus 100. Preferably, selection logic 105 includes an AND gate, and receives the logical inverse of selector input SEL[1], as well as the logical inverse of selector input SEL[2]. The output of selection logic 105 preferably controls and is received by all three multiplexers 106. It will be noted that the logical function of multiplexer cone bus 100 has again been unchanged by the illustrated restructuring. As was the case in
It should be noted that the two restructuring steps described above in connection with
The various restructuring steps illustrated in
In comparing the circuitry depicted in
First, an approximate cost of each multiplexer can be determined. A multiplexer with two data inputs (“2:1 multiplexer”) can typically be implemented using a single four-input lookup table (“4LUT”), a standard building block in PLDs. The inputs of the 4LUT include the two data inputs and the selector input of the 2:1 multiplexer.
It is well-known in the art that a multiplexer with four data inputs (“4:1 multiplexer”) can be implemented with three 2:1 multiplexers, with the outputs of two 2:1 multiplexers coupled to the data inputs of the third. Thus, a 4:1 multiplexer can easily be implemented using three 4LUTs. However, in some cases it is possible to implement a 4:1 multiplexer with only two 4LUTs. An example of such an implementation is described in U.S. patent application Ser. No. 10/728,645, filed Dec. 4, 2003, which is hereby incorporated by reference herein in its entirety. In general, the number of 4LUTs required to implement a multiplexer cone can depend on the particular implementation and topology of the cone. However, in light of the above discussion, the cost CCONE of a multiplexer cone that contains m 2:1 multiplexers can be bounded as follows:
It follows that the cost C2:1 of a 2:1 multiplexer in a multiplexer cone ranges from approximately ⅔ to approximately 1. Thus, as a conservative estimate, the lower bound of C2:1 can be approximated as follows:
The cost reduction RMUX achieved by factorizing a multiplexer bus cone of width W can be expressed as follows, taking advantage of the conservative estimate of C2:1 derived above:
Second, an approximate cost of the selection logic required by a given factorization can be determined. In the illustrative example shown in
If we let d be the average of N1 and N2 (that is, the average “distance traveled” by the electrically equivalent data inputs), CSELECTION can be rewritten as follows:
of course, the computation of the cost of selection logic will vary according to the specific implementation techniques applied, and the above estimate is used for purposes of illustration only.
Having expressed the cost reduction RMUX obtained by eliminating multiplexers and the cost CSELECTION of the added selection logic, the net cost reduction can be approximated as follows:
Thus, according to the approximations described above, factorization will yield a net cost savings if the width of the multiplexer cone bus is greater than the average distance traveled by the restructured data inputs. Such a result is consistent with the observation that factorization will be most effective when the width of the multiplexer cone bus is relatively high and the cost of the selection logic is relatively low. Viewed another way, each multiplexer cone in the bus can yield additional cost savings in the form of more eliminated multiplexers, while the selection logic can be used across all multiplexer cones in the bus, and can therefore be seen as a sort of one-time expense.
At step 506, the maximal multiplexer cones found in step 504 are preferably merged into maximal multiplexer cone buses. As used herein, a “maximal multiplexer cone bus” is a multiplexer cone bus (1) whose multiplexer cones are all maximal, and (2) to which no more multiplexer cones can be added. In an embodiment of the invention, maximal multiplexer cones can be merged into buses by computing an index for each maximal multiplexer cone, where the indices of maximal multiplexer cones that belong to the same maximal multiplexer cone bus are equal. Then, maximal multiplexer cone buses of maximal width are preferably found by sorting the maximal multiplexer cones according to their computed indices, and merging cones with equal indices into the same bus.
At step 508, the maximal multiplexer cones of step 506 are preferably factorized, using a technique such as that illustrated in
Next, method 600 preferably finds a point to which the selected data inputs can be restructured. This point is preferably between each of the selected data inputs and an output of the multiplexer cone bus. As shown in step 606, this point is preferably the convergence point of the data inputs. As used herein, a “convergence point” is defined as the point in the multiplexer cone that is farthest away from an output of the cone, and which lies between the output and each of the selected data inputs. Restructuring the data inputs to the convergence point will minimize d, the average distance traveled by the selected data inputs during factorization. As discussed above, minimizing d can result in maximizing cost savings from factorization.
At step 608, it is preferably determined whether or not factorization of the selected data inputs would reduce the cost of the multiplexer circuitry to which method 600 is applied. Although method 600 is described herein chiefly in connection with a multiplexer cone, it will be noted that such an algorithm is ideally applied to multiplexer cone buses. As discussed above, one way to determine if factorization would reduce the cost of a multiplexer cone bus is to compare the width W of the bus to the average distance d that is traveled by the selected data inputs. If W is greater than d, factorization may reduce overall cost. On the other hand, if w is less than d, factorization may not reduce overall cost.
If it is determined that factorization will reduce the cost of the multiplexer cone, the selected data inputs are preferably restructured to the convergence point at step 610, with the addition of the appropriate new multiplexer and selection logic, as illustrated by the example in
At step 706, a multiplexer is preferably added at a position closer to the output of the multiplexer cone. The added multiplexer preferably receives the same data input that was previously eliminated. For example, each of multiplexers 104 is added in
At step 708, selection logic is preferably added and coupled to the newly added multiplexer, so that the logical function of the multiplexer cone remains unchanged. For example, AND gate 103 is added in
The invention therefore advantageously reduces the cost of multiplexer circuitry. In particular, the invention can dramatically reduce the cost of multiplexer cone buses, where the cost savings increase with the width of the multiplexer cone bus. Selection logic, whose cost does not increase with the width of the multiplexer cone bus, can be added to preserve the logical function of the bus. The invention therefore is particularly effective when applied to multiplexer cone buses of relatively large width, but is not limited to such buses.
It will be noted that other embodiments of the invention aside from those described above could be used without deviating from the spirit or scope of the invention. For instance,
System 940 can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, or digital signal processing. IC 906 can be used to perform a variety of different logic functions. For example, IC 906 can be configured as a processor or controller that works in cooperation with processor 902. IC 906 may also be used as an arbiter for arbitrating access to a shared resource in system 940. In yet another example, IC 906 can be configured as an interface between processor 902 and one of the other components in system 940.
Thus it is seen that methods and apparatus are provided for reducing the cost of multiplexer circuitry. One skilled in the art will appreciate that the invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.
This application claims the benefit of provisional application No. 60/681,820, filed May 17, 2005, which is hereby incorporated by reference herein in its entirety.
Number | Name | Date | Kind |
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7002370 | Metzgen et al. | Feb 2006 | B1 |
Number | Date | Country | |
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60681820 | May 2005 | US |