Number | Date | Country | Kind |
---|---|---|---|
101 53 754 | Oct 2001 | DE |
Number | Name | Date | Kind |
---|---|---|---|
5629898 | Idei et al. | May 1997 | A |
6529433 | Choi | Mar 2003 | B2 |
Number | Date | Country |
---|---|---|
0 790 620 | Aug 1997 | EP |
Entry |
---|
Satoru Takase et al.: “A 1.6-Gbyte/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme”, IEEE Journal of Solid-State Circuits, vol. 34, No. 11, Nov. 1999, pp. 1600-1606. |
Youji idei et al.: “Dual-Period Self-Refresh Scheme for Low-Power DRAM's with On-Chip PROM Mode Register”, IEEE Journal of Solid-State Circuits, vol. 33, No. 2, Feb. 1998, pp. 253-259. |
Yasuo Miyamoto et al.: “Study of new refresh method for low data retention current”, 1993, p. 5-268. |