Embodiments of the present invention relate to resource arbitration, and more particularly a round robin arbitration scheme for resource arbitration.
When there is a resource that is shared by multiple requestors, one requestor can use the resource in a specific period (typically one clock cycle) it is necessary to have an arbiter that accepts requests and ensures that the one requestor is granted use of the resource. Examples of shared resources include a network, bus, and silicon backplane. Many situations require fair arbitration for a resource, where fair arbitration means that every requestor participating in the arbitration process should win arbitration at least one out of N arbitrations where N is the number of active requesters. In a fair arbitration scheme the worst case request-grant latency is N arbitrations for an N-requestor arbiter.
Round robin arbitration is a commonly used fair arbitration policy because it ensures equal and fair access to a resource. In a round robin arbitration policy the requestors are assigned a fixed order of priority rotation. For example, the order of three requestors could be R1, R2, R3 and back to R1. The requestor that was granted the token last is considered the lowest priority and the requester after it is considered the highest priority. For example, if R2 was the last unit to be granted a request, then R3 would be the highest priority, followed by R1 and finally R3. If R3 requests and is granted the token, then it would become the lowest priority, so the arbitration order would be R1, R2, then R3.
Another form of round robin arbitration uses a ring counter to cycle the priority of each of the requestors by selecting one of N fixed-priority arbiters. Every time a request is granted the ring counter advances by one. This approach is less desirable in many applications than the approach above where the requester is made the lowest priority, because it doesn't distribute the bandwidth as evenly when there are inactive requesters.
One prior art implementation of a combinational logic block arbitration mechanism at least three levels deep to determine a request to grant delay time is illustrated in
A method and apparatus for a fair resource arbitration scheme is described. An arbitration unit that implements a fair round robin policy where each requesting device has an equal chance of accessing a shared resource based upon a rotating request priority assigned to that requesting device, wherein the fast arbitration unit includes a plurality of state registers, one for each possible unordered pair of requesting devices.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
a illustrates an example table of how an embodiment of the round robin arbitration may process amongst three devices A, B, and C.
b illustrates a block diagram of an embodiment of arbitrator to implement a round robin arbitration policy.
a illustrates an embodiment of a state block and an arbiter update logic block.
b illustrates Table 2, which shows an example next state with the device arbiter.
In the following description, numerous specific details are set forth, such as examples of specific data signals, named components, connections, number and type of logic circuits making up arbitration logic, etc., in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known components or methods have not been described in detail but rather in a block diagram in order to avoid unnecessarily obscuring the present invention. Thus, the specific details set forth are merely exemplary. The specific details may be varied from and still be contemplated to be within the spirit and scope of the present invention.
In general, a method and apparatus for a round robin arbitration is described. Arbitration for a shared resource can be important to the performance of many systems. A round-robin arbiter may be desired so all requesters are guaranteed a uniform share of access to the resource being managed by the arbiter. A fast request to grant may be desired for fast system performance by limiting the combinational logic to two or less levels deep. The combinational logic being two or less levels deep creates a round robin arbitration scheme for resource arbitration with a minimal delay time in the combinational logic to compute the grant output.
a illustrates an example table of how an embodiment of the round robin arbitration may process amongst three devices A, B, and C. Table 1 illustrates how the round robin arbiter changes grants 203 to the highest priority requester 205 based on its current state and updates its state to decrease the priority of the granted device. Note that merely N states are possible in a N-device round robin implementation. The arbitration state 201 describes the order in which the devices are prioritized. ABC means that A will win arbitration if it requests, B will win arbitration only if A isn't requesting, and C will win arbitration only if A and B aren't requesting. In this three device round robin arbitration case, priority orders of ABC, BCA, and CAB are possible (with the last device to win an arbitration being at the end of the list). As the number of devices connected to the arbiter increases, the number of rotations increases linearly (N), but the number of pair-wise state bits increases quadratically (N*(N−1)/2).
b illustrates a block diagram of an embodiment of arbitrator to implement a round robin arbitration policy. The fast arbitration unit 202 implements a fair, not predisposed, arbitration policy where each requesting device has an equal chance (over a some small window of arbitrations) of accessing a shared resource based upon the current request priority assigned to that requesting device. The fast arbitration unit 202 includes three parts, an arbiter update logic block 204, an arbiter state block 206, and an arbiter output logic block 208. The arbiter update logic block 204 updates the request priority of the potential requesting devices. The arbiter state block 206 stores the request priority of each potential requesting device relative to every other requesting device. The arbiter output logic block 208 determines, which request will be granted. This block features a low request to grant logic delay time. All of the devices participating in this arbitration cycle send their request to use the shared resource to the arbiter output logic block 208. A plurality of state registers in the arbiter state block 206 supplies relative request priority information to logic gates in the arbiter output logic block 208.
The fast arbitration unit 202 implementing the arbitration policy attempts to guarantee fairness with no starvation among requesting devices. The fast arbitration unit 202 implementing the round robin arbitration policy chooses all elements in a group equally in some rational order, typically with a rotating priority scheme where each device is the top priority device at some time in the round robin arbitration cycle. The round robin rotation may either be a simple one device rotation of the priority (e.g. advancing from ABC to BCA when any unit wins arbitration or a time slot passes) or it may involve advancing the rotation to the point where the winning device is now the lowest priority (e.g. advancing from ABC to BCA if A wins, but advancing to ABC if C wins). The fast arbitration unit 202 implementing the round robin arbitration policy grants access to the resource to the requesting device 1) with the highest priority and 2) who also sends a request to access the shared resource.
In the arbiter state block 206, a state register may exist for each possible pair of requesting devices. Each state register may store 1) the arbitration servicing information, such as request priority information, for a particular requesting device and 2) how that device's arbitration servicing information compares to another potential requesting device's arbitration servicing information in order to determine which of these two devices has a higher request priority between them. Thus, each state register stores which of the pair of requests will win if both are requesting. The arbiter state block 206 supplies the inputs to the logic gates of the combinational logic block in coordination with the actual requests present during that arbitration cycle to determine which requesting device will be granted the token ownership of the shared resource for an arbitration cycle. The actual request to grant delay time may be improved by moving more of the computational activities to the arbiter state block 206 and arbiter update logic block 204.
One state register is needed for any unordered pair of requests rather than an ordered pair of requests because the either the true output or the complement output of the state register describe both ordered pairs. Thus the number of state registers required is N*(N−1)/2 where N is the number of requesting devices. Referring to
Each state register may receive an input indicating recent arbitration servicing information for all of the potential requesting devices from the arbiter update logic block 204. The arbiter update logic block 204 supplies an input to update the request priority between each pair of requesting devices for every status register in the arbiter state block even the status registers associated with a pair of potential requesting devices that did not win the arbitration process.
a and 4b illustrate the round robin rotation policy.
This logic structure can be generalized and applied to resources where there are more than three example requesting devices shown in the figures. In this case additional inputs, requesting pair state registers, arbiter update logic, and arbiter output logic may be required, but it all follows the pattern seen in the example three device arbiter. The number of state registers required for a N-requestor arbiter is N*(N−1)/2.
A reliable prediction of the worst-case wait time is another advantage of the round-robin protocol. The worst-case wait time is proportional to number of requestors minus one.
In addition, the fast arbitration unit may be employed in other implementations such as memory scheduling.
In an embodiment, a machine-readable medium may have stored thereon information representing the apparatuses and/or methods described herein. A machine-readable medium includes any mechanism that provides (e.g., stores and/or transmits) information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; DVD's, EPROMs, EEPROMs, FLASH, magnetic or optical cards, or any type of media suitable for storing electronic instructions. Slower mediums could be cached to a faster, more practical, medium. The information representing the apparatuses and/or methods stored on the machine-readable medium may be used in the process of creating the apparatuses and/or methods described herein. For example, the information representing the apparatuses and/or methods may be contained in an Instance, soft instructions in an intellectual property (IP) generator, or similar machine-readable medium storing this information. Thus, the information representing the apparatuses and/or methods stored on the machine-readable medium may be used in the process of creating the apparatuses and/or methods described herein.
The IP generator may be used for making highly configurable, scalable System On a Chip inter-block communication system that integrally manages data, control, debug and test flows, as well as other applications. In an embodiment, an example intellectual property generator may comprise the following: a graphic user interface; a common set of processing elements; and a library of files containing design elements such as circuits, control logic, and cell arrays that define the intellectual property generator.
In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, in one embodiment, the arbitration policy may be implemented in hardware with logic gates. In another embodiment, the arbitration policy may be implemented in software. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
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