Arnold O. Allen, Probability, Statistics, and queueing Theory With Computer Science Applications, Second Edition, Academic Press, Inc., pp. 450, 458-459,. (Nov. 1990). |
Harold Pilo, Steve Lamphier, Fred Towler, Richard Hee, A 300 MHz, 3.3V 1Mb SRAM Fabricated in a 0.5.mu.m CMOS Process,IBM Microelectronics Division, Essex Junction, VT, pp.148-149, 1996 IEEE International Solid-State Circuits Conference (Feb. 9,1996). |
PCT International Search Report, PCT/US 97/09219, dated Jun.10,1997. |
T. Yang, M. Horowitz, and B. Wooley, "A 4-ns 4K.times.1-bit Two Port BiCMOS SRAM", IEEE Journal of Solid State Circuits, vol. 23, No. 5, pp. 1030-40 (Oct. 1988). |
T. Chappell, et al., "A2ns Cycle, 4ns Access 512kb CMOS ECL SRAM", IEEE International Solid-State Circuits Conference, pp. 50-51 (1991). |
Translated Abstract of Japanese patent application No. 58-54412, vol. 7, No. 138 (P-204) (1283) Jun. 16, 1983. |
H. Shumacher, J. Dikken, and E. Seevinck, "CMOS Subnanosecond True-ECL Output Buffer", IEEE Journal of Solid-State Circuits, vol. 25, No. 1, pp. 148-154 (Feb. 1990). |