Method and apparatus for space vector modulation in multi-level inverters

Abstract

An apparatus for space vector modulation of a multi-level inverter, the apparatus comprising: a triangle generator for finding a modulation triangle enclosing a reference voltage vector, the modulation triangle comprising vertex vectors; a duty ratio calculator for determining duty ratios for the vertex vectors; a switching function selector for selecting switching functions corresponding to the vertex vectors; a forbidden transition identifier for identifying a forbidden transition between two of the vertex vectors; and a control module for applying the switching functions to the multi-level inverter according to the duty ratios and avoiding the forbidden transition.

Description

BACKGROUND

The present invention relates generally to the field of power conversion electronics and more specifically to the field of space vector modulation for multi-level inverters.

A multi-level inverter is an assemblage of electronically controllable switches coupling a multi-level direct current (DC) input bus to an alternating current (AC) output bus. Often, the AC output bus will comprise multiple output phases.

Nominally, the controllable switches are operated either fully open or fully closed. Under such operation, the only instantaneous output voltages the inverter can produce are those levels available at the DC input bus. Rapid switching between different instantaneous output voltages is often used, therefore, to produce an output whose time average is intermediate to the DC input bus levels. When multiple output phases are produced, each switch closure combination produces a pattern of output voltages across the phases which may be thought of as being distributed in space. Hence, the patterns of output voltages are termed “space vectors,” and the rapid switching scheme is known as “space vector modulation” or “space vector pulse width modulation.”

Compared to two-level inverters, multi-level inverters promise many advantages including reduced voltage and current harmonics at relatively lower switching frequencies and reduced voltage rating requirements for the controllable switches. However, the increased number of DC input bus levels implies an increased number of controllable switches. The mapping (switching function) from desired (reference) space vectors to switch closure combinations is typically not unique. Furthermore, with a larger number of controllable switches, injudicious modulation strategies may result in unacceptably high switching losses.

Opportunities exist, therefore, to find new space vector modulation techniques to resolve the ambiguity inherent in the non-uniqueness of the switching function and to efficiently utilize the controllable switches to reduce switching losses.

SUMMARY

The opportunities described above are addressed, in one embodiment of the present invention, by an apparatus for space vector modulation of a multi-level inverter, the apparatus comprising: a triangle generator for finding a modulation triangle enclosing a reference voltage vector, the modulation triangle comprising vertex vectors; a duty ratio calculator for determining duty ratios for the vertex vectors; a switching function selector for selecting switching functions corresponding to the vertex vectors; a forbidden transition identifier for identifying a forbidden transition between two of the vertex vectors; and a control module for applying the switching functions to the multi-level inverter according to the duty ratios and avoiding the forbidden transition.

DRAWINGS

These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:

FIG. 1 illustrates a switching function for a three-level, three-phase inverter.

FIG. 2 illustrates a skew coordinate representation for space vectors of a three-level, three-phase inverter.

FIG. 3 illustrates a block diagram of one embodiment of the present invention.

DETAILED DESCRIPTION

By way of example, not limitation, FIG. 1 illustrates a switching function for a three-phase, three-level inverter, with the levels equally spaced. The A, B, and C axes correspond to the three AC output phases. The space vector Vref can be thought of as a phasor rotating counterclockwise with constant angular speed. The projections of Vref onto A, B, and C represent sinusoidally varying voltages with amplitudes equal to the length of Vref, frequencies equal to the angular speed of Vref, and phases such that B lags A by 120 degrees and C lags B by 120 degrees. The numbers in brackets denote the three inverter phase output voltages divided by the DC input level spacing. For example, if the spacing between DC input levels is 10V, then triplet labels the point slightly below and to the left of the left bracket at a vertex of the dashed-line triangles. It will be obvious to one of ordinary skill in the art that the diagram of FIG. 1 can be expanded radially to include additional DC bus input levels.

To illustrate the inherent switching function non-uniqueness, note that, for example, the point is also equivalent to [1, 2, 2]. That is, taking one step along the B direction followed by one step along the C direction takes you to the same point as taking one step along A, two steps along B, and then two steps along C. Similarly, the origin is equivalent to [0, 0, 0], [1, 1, 1], and [2, 2, 2].

To illustrate the difference in efficiency among switching policies, note that synthesizing the time average value of Vref shown entails modulating among V₁=[1,0,0], V₂=[1,0,1], and V₃=[2,0,1]. If we choose the pattern V₁,V₂,V₃,V₁,V₂,V₃, then each repetition of the pattern requires six changes of switch state. If, in contrast, we choose the pattern V₁,V₂,V₃,V₃,V₂,V₁, then each repetition of the pattern requires only four changes of switch state and produces the same voltage with reduced switching loss.

Continuing the example of FIG. 1, FIG. 2 illustrates a skew coordinate representation for space vectors of the same three-level, three-phase inverter. It is well known to those skilled in the art that a two-axis representation using G and H axes, as shown, where G coincides with the A axis and H coincides with the negative C axis, significantly simplifies some of the intermediate space vector modulation calculations. Each parenthetical, ordered (G, H) pair labels the point slightly below and to the left of the left parenthesis at a vertex of the dashed-line triangles. The representation is referred to as a “skew coordinate representation” because G and H are not orthogonal.

In one embodiment of the present invention, FIG. 3 illustrates a block diagram of an apparatus 100 for space vector modulation of a multi-level inverter. Apparatus 100 comprises a triangle generator 110, a duty ratio calculator 120, a switching function selector 130, a forbidden transition identifier 140, and a control module 150. In operation, triangle generator 110 finds a modulation triangle enclosing a given reference voltage vector. For the three vertex vectors that delineate the modulation triangle, duty ratio calculator 120 determines the duty ratios required to reproduce the reference voltage vector. Switching function selector 130 then resolves any switching function ambiguity by selecting a switching function (i.e., a pattern of switch closures) corresponding to the vertex vectors. As the example of FIG. 1 illustrated, switching losses can be reduced if certain vector transitions are forbidden; hence, forbidden transition identifier 140 identifies a forbidden transition between two of the vertex vectors. Finally, control module 150 applies the selected switching functions to the multi-level inverter, according to the duty ratios found, and in an order that avoids the forbidden transition.

In a more detailed embodiment of the present invention, FIG. 3 also illustrates apparatus 100 wherein the switching function selector 130 comprises a vertex level computer 160, a triangle level computer 170, and a switching function computer 180. In operation, vertex level computer 160 compute a vertex level, L, for each of the vertex vectors. If a vertex vector is described by the skew coordinate pair (G, H), then L, is computed according to the rule

$\begin{array}{c}L=\{\begin{array}{c}\mathrm{abs}\left(H\right),\mathrm{if}G=0\mathrm{or}G+H=0\\ \mathrm{abs}\left(G\right),\mathrm{if}H=0\\ H\sin \left(2\pi /3\right)/\sin \left(T\right),\mathrm{otherwise}\end{array}\mathrm{where}\\ T={\tan }^{-1}\left(\frac{H\sin \left(2\pi /3\right)}{G+H\cos \left(\pi /3\right)}\right)\end{array}$ and “abs ( )” denotes the absolute value function.

Triangle level computer 170 then computes a triangle level, K, equal to the maximum of the individual vertex levels. Taking K as input, switching function computer 180 computes the switching functions, V, to the rule

$V=\{\begin{array}{c}\begin{array}{c}\left[K,\mathrm{abs}(K-\mathrm{abs}\left(G\right),\mathrm{abs}\left(K-\mathrm{abs}\left(G\right)-\mathrm{abs}\left(H\right)\right)\right],\\ \mathrm{if}G>0\mathrm{and}\left(G+H\right)>0\end{array}\\ \left[\mathrm{abs}\left(K-\mathrm{abs}\left(G\right)\right),K,\mathrm{abs}\left(K-\mathrm{abs}\left(H\right)\right)\right],\mathrm{if}G<0\mathrm{and}H>0\\ \begin{array}{c}\left[\mathrm{abs}\left(K-\mathrm{abs}\left(G\right)-\mathrm{abs}\left(H\right)\right),\mathrm{abs}\left(K-\mathrm{abs}\left(H\right)\right),K\right],\\ \mathrm{if}H<0\mathrm{and}\left(G+H\right)<0\end{array}\end{array}$

In another more detailed embodiment, also illustrated in FIG. 3, forbidden transition identifier 140 comprises a forbidden transition module 190. In operation, forbidden transition module 190 identifies a forbidden transition between two of the vertex vectors. If a first vertex vector has skew coordinates (G₁, H₁), and a second vertex vector has skew coordinates (G₂, H₂), then the transition between the two vectors is forbidden if(G₁>0 and G₁+H₁>0 and G₂>0 and G₂+H₂>0 and H₁−H₂=0)or(G₁<0 and H₁>0 and G₂<0 and H₂>0 and G₁−G₂+H₁−H₂=0)or(H₁<0 and G₁+H₁<0 and H₂<0 and G₂ +H₂<0 and G₁−G₂=0)

In another more detailed embodiment, also illustrated in FIG. 3, control module 150 is configured to avoid the forbidden transition as follows: if the switching functions are denoted respectively as V₁,V₂,V₃, with the identified forbidden transition being between V₁, and V₃, then repeating the switching functions in the order V₁, V₂, V₃, V₃, V₂, V₁, avoids the forbidden transition.

All of the elements described above of embodiments of the present invention may be implemented, by way of example, but not limitation, using singly or in combination any electric or electronic devices capable of performing the indicated functions. Examples of such devices include, without limitation: analog devices; analog computation modules; digital devices including, without limitation, small-, medium-, and large-scale integrated circuits, application specific integrated circuits (ASICs), and programmable logic arrays (PLAs); and digital computation modules including, without limitation, microcomputers, microprocessors, microcontrollers, digital signal processors (DSPs), and programmable logic controllers (PLCs).

In some embodiments, the elements described above of the present invention are implemented as software components in a general purpose computer. Such software implementations produce a technical effect of modulating the space vector of a multi-level inverter.

While only certain features of the invention have been illustrated and described herein, many modifications and changes will occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.

Claims

1. An apparatus for space vector modulation of a multi-level inverter, said apparatus comprising: a triangle generator for finding a modulation triangle enclosing a reference voltage vector, said modulation triangle comprising vertex vectors;a duty ratio calculator for determining duty ratios for said vertex vectors;a forbidden transition identifier for identifying a forbidden transition between two of said vertex vectors;a control module for applying said switching functions to said multi-level inverter according to said duty ratios and avoiding said forbidden transition; anda switching function selector for selecting switching functions corresponding to said vertex vectors, wherein said switching function selector comprises:a vertex level computer for computing vertex levels corresponding to said vertex vectors, each of said vertex vectors being described by a respective skew coordinate pair, (G, H), each of said vertex levels, L, being computed according to the rule:

2. The apparatus of claim 1 wherein said forbidden transition identifier comprises: a forbidden transition module for identifying as forbidden a transition between a first vertex vector, having skew coordinates (G1,H1), and a second vertex vector, having skew coordinates (G2,H2) if (G1>0 and G1+H1>0 and G2>0 and G2+H2>0 and H1−H2=0)or(G1<0 and H1>0 and G2<0 and H2>0 and G1−G2+H1−H2=0)or(H1<0 and G1+H1<0 and H2<0 and G2+H2<0 and G1−G2=0).

3. The apparatus of claim 1 wherein said control module is configured for performing the acts of: denoting said switching functions respectively as V1, V2, V3, said forbidden transition being between V1 and V3; andrepeating said switching functions in the order V1, V2, V3, V3, V2, V1.

4. An apparatus for space vector modulation of a multi-level inverter system, said apparatus comprising: a triangle generator for finding a modulation triangle enclosing a reference voltage vector, said modulation triangle comprising vertex vectors;a duty ratio calculator for determining duty ratios for said vertex vectors;a switching function selector for selecting switching functions corresponding to said vertex vectors;a forbidden transition identifier for identifying a forbidden transition between two of said vertex vectors; anda control module for applying said switching functions to said multi-level inverter according to said duty ratios and avoiding said forbidden transition,said switching function selector comprising:a vertex level computer for computing vertex levels corresponding to said vertex vectors, each of said vertex vectors being described by a respective skew coordinate pair, (G, H), each of said vertex levels, L, being computed according to the rule:

5. The apparatus of claim 4 wherein said control module is configured for performing the acts of: denoting said switching functions respectively as V1, V2, V3, said forbidden transition being between V1 and V3; andrepeating said switching functions in the order V1, V2, V3, V3, V2, V1.

6. A method of space vector modulation for a multi-level inverter system, said method comprising the acts of: finding a modulation triangle enclosing a reference voltage vector, said modulation triangle comprising vertex vectors;determining duty ratios for said vertex vectors;selecting switching functions corresponding to said vertex vectors;identifying a forbidden transition between two of said vertex vectors;applying said switching functions to said multi-level inverter according to said duty ratios and avoiding said forbidden transition; andselecting switching functions corresponding to said vertex vectors, such act comprising:computing vertex levels corresponding to said vertex vectors, each of said vertex vectors being described by a respective skew coordinate pair, (G, H), each of said vertex levels, L, being computed according to the rule:

7. The method of claim 6 wherein said act of identifying a forbidden transition between two of said vertex vectors comprises: identifying as forbidden a transition between a first vertex vector, having skew coordinates (G1,H1), and a second vertex vector, having skew coordinates (G2,H2) if (G1>0 and G1+H1>0 and G2>0 and G2+H2>0 and H1−H2=0)or(G1<0 and H1>0 and G2<0 and H2>0 and G1−G2+H1−H2=0)or(H1<0 and G1+H1<0 and H2<0 and G2+H2<0 and G1−G2=0).

8. The method of claim 6 wherein said act of applying said switching functions to said multi-level inverter comprises: denoting said switching functions respectively as V1, V2, V3, said forbidden transition being between V1 and V3; andrepeating said switching functions in the order V1, V2, V3, V3, V2, V1.