BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic of a tuning support apparatus according to an embodiment of the present invention;
FIG. 2 is a block diagram of the tuning support apparatus according to the embodiment;
FIG. 3 is a flowchart of a program creating process by a multi-core processor;
FIG. 4 is a schematic for illustrating granularity information of Task1;
FIG. 5A is a schematic for illustrating a program list of func1 of Task1 shown in FIG. 4;
FIG. 5B is a schematic for illustrating a program list of func2 of Task1 shown in FIG. 4;
FIG. 5C is a schematic for illustrating a program list of func3 of Task1 shown in FIG. 4;
FIG. 6 is a schematic for illustrating granularity information of Task2;
FIG. 7A is a schematic for illustrating a program list of funcm of Task2 shown in FIG. 6;
FIG. 7B is a schematic for illustrating a program list of funcn of Task2 shown in FIG. 6;
FIG. 8 is a schematic for illustrating granularity information of Task3;
FIG. 9A is a schematic for illustrating a program list of funca of Task3 shown in FIG. 8;
FIG. 9B is a schematic for illustrating a program list of funcb of Task3 shown in FIG. 8;
FIG. 9C is a schematic for illustrating a program list of funcc of Task3 shown in FIG. 8;
FIG. 9D is a schematic for illustrating a program list of funcd of Task3 shown in FIG. 8;
FIG. 9E is a schematic for illustrating a program list of funce of Task3 shown in FIG. 8;
FIG. 9F is a schematic for illustrating a program list of funcf of Task3 shown in FIG. 8;
FIG. 10 is a schematic for illustrating granularity information of Task4;
FIG. 11 is a schematic for illustrating a program list of funcx of Task4 shown in FIG. 10;
FIG. 12 is a table of structure information of Task1 to Task4;
FIG. 13 is a table of dependence information of Task1 to Task4;
FIG. 14A is a schematic for explaining a degree of dependence of Task1;
FIG. 14B is a schematic for explaining a degree of dependence of Task1;
FIG. 15 is a table of load definition;
FIG. 16 is a schematic of an example of a display screen;
FIG. 17 is a schematic of a display example of a result of diagnosis;
FIG. 18 is a schematic of a display example of a result of diagnosis;
FIG. 19A is a schematic for illustrating an example of a tuning process;
FIG. 19B is a schematic for illustrating an example of the tuning process; and
FIG. 20 is a schematic for illustrating an example of the tuning process.