BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a schematic diagram of a known four-transistor (4-T) buried gated photodiode device commonly referred to as a 4-T pinned photodiode pixel.
FIG. 2 illustrates a timing diagram that demonstrates the timing of events during operations of the pixel shown in FIG. 1.
FIG. 3 illustrates a schematic diagram of a pixel that uses the analog sampling circuit of the invention to reduce or eliminate random telegraph noise.
FIG. 4 illustrates a timing diagram that demonstrates the timing of events during operations of the pixel shown in FIG. 3.
FIG. 5 illustrates a flowchart that represents the method of the invention in accordance with an exemplary embodiment.
DETAILED DESCRIPTION OF AN EXEMPLARY EMBODIMENT
In accordance with the invention, an analog sampling circuit comprising a plurality of capacitors is used to sample the reset and video sampling levels at different instants in time to obtain average reset and video sampling values. By averaging the reset and video sampling levels over time, random telegraph noise in the reset and video sampling values is eliminated or at least substantially reduced.
FIG. 3 illustrates a schematic diagram of a pixel 22 having an output that is connected to an analog sampling circuit 50 of the invention. The analog sampling circuit 50 comprises a reset sampling circuit 60 and a video sampling circuit 70. In accordance with this exemplary embodiment, eight capacitors 62-69 are used in the reset sampling circuit 60 to sample the reset sampling level of the pixel 22 over respective timing intervals during the reset sampling period. These reset sampling values are then averaged to produce a reduced-noise reset sampling value, i.e., a reset sampling value from which random telegraph noise has been removed. Likewise, eight capacitors 82-89 are used in the video sampling circuit 70 to sample the video sampling level of the pixel 22 over respective timing intervals during the video sampling period. These video sampling values are then averaged to produce a reduced-noise video sampling value.
The reset sampling circuit 60 employs a switching configuration comprising switches S1 Global and switches S1(1)-S1(8). The video sampling circuit 70 employs a switching configuration comprising switches S2 Global and switches S2(1)-S2(8). The components 23, 24, 25, 26, 27, 28, 29 and 31 of the pixel 22 may be identical to the components 3, 4, 5, 6, 7, 8, 9 and 11 of the pixel 2 shown in FIG. 1. The analog readout column line 33 and the current source 34 shown in FIG. 3 may be identical to the analog readout column line 12 and the current source 13 shown in FIG. 1.
As stated above, the pixel 2 shown in FIG. 1 is a 4-T buried gated photodiode device. While the invention is suitable for use with this type of photodiode device, the invention is not limited with respect to the type of photodiode device with which the invention is implemented. The invention is being described with reference to a 4-T buried gated photodiode device for exemplary purposes and to demonstrate the principles and concepts of the invention.
The manner in which the pixel 22 and analog sampling circuit 50 operate will now be described with reference to FIG. 3 and with reference to the timing diagram shown in FIG. 4. To sample the pixel 22, the Row control signal 29 is asserted high. When the reset sampling signal S1 Global goes high, S1 Global switch is closed. When S1 Global goes high, all of the individual S1 sampling signals S1(1)-S1(8) also go high, causing all of the switches S1(1)-S1(8) to close. The RST control signal 27 goes high just after the signals S1 Global and S1(1)-S1(8) go high. The TX control signal 28 and the video sampling signals S2 Global and S2(1)-S2(8) are all low at this time. When the RST control signal 27 is high, the RST transistor 23 is on and the FD node 32 is connected to the power supply, VDD, which turns on the source follower (SF) transistor 24 and causes a buffered voltage corresponding to the voltage on the FD node 32 to be driven onto the analog readout column line 33. The capacitors 62-69 are then disconnected by opening the S1(1)-S1(8) switches one at a time, as indicated in the timing diagram by the S1(1)-S1(8) signals going low one at a time. Thus, each of the capacitors 62-69 samples the reset sampling value from the analog readout column line 33 over a respective timing interval during the reset sampling period. Subsequent to this sampling sequence, the global switch S1 GLOBAL is opened and all of the S1(1)-S1(8) switches are closed simultaneously (not shown), thereby causing the values stored on the capacitors 62-69 to be redistributed such that each capacitor has an average reset sampling value stored on it. This average reset sampling value contains a reduced level of random telegraph noise and is subsequently used by circuitry downstream (not shown) to obtain the difference between the average reset and average video sampling values.
After reset sampling signals S1 Global and S1(1)-S1(8) go low, the video sampling signals S2 Global and S2(1)-S2(8) go high, causing the S2 Global switch and the S2(1)-S2(8) switches to close. The TX control signal 28 then goes high. The RST control signal 27 and the reset sampling signals S1 Global and S1(1)-S1(8) are all low at this time. When the TX control signal 28 goes high, the TX transistor 25 is turned on, connecting the photodiode 31 to the FD node 32. Charge that had been previously integrated on the photodiode 31 due to light is transferred to the FD node 32 at this time. The SF transistor 24 is turned on, causing the video sampling value, which corresponds to the value of the voltage on the FD node 32 at this time, to be driven onto the analog readout column line 33. The capacitors 82-89 are then disconnected one at a time by opening the S2(1)-S2(8) switches one at a time, as indicated in the timing diagram by the S2(1)-S2(8) signals going low one after the other. Thus, each of the capacitors 82-89 samples the video sampling value over a respective timing interval during the video sampling period. Subsequent to this sampling process, the global switch S2 Global is opened and all of the S2(1)-S2(8) switches are closed simultaneously (not shown), thereby causing the values stored on the capacitors 82-89 to be redistributed such that each capacitor has an average video sampling value stored on it. This average video sampling value has a reduced level of random telegraph noise and is subsequently used by circuitry downstream (not shown) to obtain the difference between the average reset and average video sampling values.
In FIG. 3, the analog sampling circuit 50 is shown as having eight reset sampling capacitors 62-69 and eight video sampling capacitors 82-89. The invention is not limited to the configuration shown. Any configuration that is capable of sampling the reset and video levels over time and averaging the sampling values to obtain average reset and video sampling values is suitable for achieving the goals of the invention. One of the advantages of the configuration of the analog sampling circuit 50 shown in FIG. 3 is that it generally requires the same amount of area on the IC as that required by the components 14-17 shown in FIG. 1. This is because each of the capacitors 62-69 consumes only one eighth of the amount of space consumed by the capacitor 15, i.e., all of the capacitors 62-69 combined consume the same amount of area as that consumed by the single capacitor 15. Likewise, each of the capacitors 82-89 consumes only one eighth of the amount of space consumed by the capacitor 17, i.e., all of the capacitors 82-89 combined consume the same amount of area as that consumed by the single capacitor 17. Consequently, the invention provides a solution for eliminating or at least substantially reducing random telegraph noise that does not increase the overall size of the image sensor device and does not reduce the fill factor of the image sensor device.
FIG. 5 illustrates a flowchart that demonstrates the method of the invention in accordance with an exemplary embodiment. A reset sampling level on an output of a pixel is sampled at different instants in time during a reset sampling phase to obtain a plurality of respective reset sampling values, as indicated by block 101. The reset sampling values are averaged to produce an average reset sampling value, as indicated by block 102. A video sampling level on the output of the pixel is sampled at different instants in time during a video sampling phase to obtain a plurality of respective video sampling values, as indicated by block 103. The video sampling values are averaged to produce an average video sampling value, as indicated by block 104. It should be noted that the invention is not limited with respect to the order in which the steps represented by blocks 101-104 are performed. For example, the steps represented by blocks 103 and 104 may be performed before the steps represented by blocks 101 and 102 are performed.
It should be noted that the invention has been described with reference to a few example embodiments and that the present invention is not limited to these embodiments. The embodiments described herein are meant to convey the principles and concepts of the present invention and are not intended to demonstrate exclusive embodiments for carrying out the invention. For example, the invention is not limited to the particular configuration shown in FIG. 3 or to the timing of events represented by the timing diagram shown in FIG. 4. Other modifications may be made to the embodiments described herein and all such modifications are within the scope of the present invention.
Patent Application
20080062286
