Patent Application
20070268895
Embodiments of the invention will be described, by way of example only, with reference to the drawings, in which
The following description focuses on embodiments of the invention applicable to a GSM cellular communication system. However, it will be appreciated that the invention is not limited to this application but may be applied to many other networks or communication systems wherein switching of data between input and output connections is performed.
Further description of the GSM/communication system can be found in ‘The GSM System for Mobile Communications’ by Michel Mouly and Marie Bernadette Pautet, Bay Foreign Language Books, 1992, ISBN 2950719007.
In the example of
The first base station 105 is coupled to a first Base Station Controller (BSC) 107. A BSC performs many of the control functions related to the air interface including radio resource management and routing of data to and from appropriate base stations.
The first BSC 107 is coupled to a core network 109. A core network interconnects BSCs and is operable to route data between any two BSCs, thereby enabling a remote station in a cell to communicate with a remote station in any other cell. In addition, a core network comprises gateway functions for interconnecting to external networks such as the Public Switched Telephone Network (PSTN), thereby allowing remote stations to communicate with landline telephones and other communication terminals connected by a landline. Furthermore, the core network comprises much of the functionality required for managing a conventional cellular communication network including functionality for routing data, admission control, resource allocation, subscriber billing, remote station authentication etc.
The core network 109 is further coupled to a second BSC 111 which is coupled to a second base station 113. The second base station 113 supports a third remote station 115.
In order to establish links between the remote stations 101, 103, 115 (or an external network), the core network 109 comprises one or more switches that is capable of establishing links between a number of input connections and output connections. In the specific example, the core network 109 comprises a switch 117 to which the BSCs 107, 111 are coupled (it will be appreciated that although
The switch 117 comprises a number of line termination boards 201, 203, 205. Each of the line termination boards 201, 203, 205 receives one or more E1 lines 207 from BSCs of the system. Specifically, a first line termination board 201 is coupled to the first BSC 107 by an E1 line and a second line termination board 203 is coupled to the second BSC 111 by another E1 line. Each of the E1 lines thus support a large number of connections corresponding to the active remote stations served by the associated BSC.
Thus, the line termination boards 201-205 receive and transmit call data to and from the individual BSCs 107,111. The E1 lines use a time division multiplexing system wherein time frames are divided into a number of time slots with individual time slots being allocated to individual remote stations 101, 103, 115. Specifically, each time slot can accommodate a pulse code modulated speech sample for a given voice call. For an E1 line of a GSM cellular communication system, each time slot is typically 125 μs. Thus, in the example, the connections supported by the E1 line correspond to time slots.
The line termination boards 201-205 are coupled together via a network 209. In the specific example, the network 209 is an Ethernet network but it will be appreciated that in other embodiments other interconnecting fabrics may be used and that the network may for example utilise a star or mesh configuration.
In the switch 117 of
The switch 117 furthermore comprises a switch controller 211 which is coupled to the Ethernet network 209. The switch controller 211 receives connection information which determines which of the input connections should be switched to which output connections. For example, the switch controller 211 can receive information which indicates that a circuit switched setup of a call between the first remote station 101 and the third remote station 115. Accordingly the switch controller 211 determines that a time slot of the E1 line from the first BSC 107 of the first line termination board 201 should be switched to the time slot assigned to the third remote station 115 on the E1 line from the second BSC 111 to the second line termination board 203.
In operation, the switch controller 211 communicates information to the line termination boards 201-205 that informs these of the destination for the data of the input E1 lines. For example, the first line termination board 201 is informed that the data of the time slot of the first remote station 101 should be sent to the second line termination board 203.
In operation, the switch 117 of
Within each Epoch, each of the line termination boards 201-205 combine all the data which is to be transmitted to another of the line termination boards 201-205. Thus in each Epoch, the first line termination board 201 selects all the data from the incoming E1 lines which are to be forwarded to E1 lines of the second line termination board 203. This data is combined into a block of data which is then transmitted to the second line termination board 203. Similarly, within each Epoch the first line termination board 201 selects the incoming data for each of the other line termination boards 205 and transmits this data to the appropriate line termination board 205. Thus, within each Epoch the data is divided into data blocks for the different line termination boards and each data block is transmitted over the Ethernet network 209 to the appropriate destination line termination board.
In addition, the line termination boards 201-205 generate mapping data which is indicative of the destination of the data for each line termination board. Specifically, the first line termination board 201 generates mapping data for the second line termination board 203. This mapping data indicates which specific time slots on which specific E1 lines the individual data values should be allocated to. This mapping data is also transmitted from the first line termination board 201 to the second line termination board 203 via the Ethernet network 209. Similarly, mapping data is generated for the other line termination boards 205 and transmitted to these.
In each Epoch, the line termination boards 201-205 thus receive a data block and mapping data from each of the other line termination boards 201-205. In response, the line termination board 201-205 proceeds to allocate the user data of the data block to the appropriate time slots on the appropriate E1 lines 207. This allocation is performed in response to the mapping data which is received from the originating line termination board 201-205.
It will be appreciated that in the specific described embodiments the mapping data generation is performed at the individual line termination boards 201-205 but that in other embodiments the mapping data may be generated elsewhere than in the switch 117 such as for example in the switch controller.
The switch 117 provides a number of advantages over conventional switching technologies. For example, standardised and general purpose hardware and software, such as Ethernet hardware and software, can be used thereby reducing cost substantially. In particular, efficient switch performance can be achieved without the requirement for a real time switch matrix to be implemented.
The first line termination board 201 comprises an E1 interface 301 which interfaces to the E1 line from the first BSC 107. The E1 interface 301 is coupled to a data buffer 303 which can store all the data received within an Epoch.
The first line termination board 201 furthermore comprises an Ethernet interface 305 which is arranged interface to the Ethernet network 209 connecting the line termination boards 201-205. Specifically, the Ethernet interface 305 can transmit data messages over the Ethernet network 209 to the other line termination boards 201-205.
The data buffer 303 is coupled to a data block processor 307 which for each Epoch combines the data of the input time slots that is to be switched to an E1 line of the second line termination board 203. The data is combined into a data block, which in the example comprises only traffic data and does not comprise any switching data that is indicative of which output timeslots or E1 lines the data should be switched to. Indeed, the data block may consist only of the in-call data. The data block processor 307 is furthermore coupled to the Ethernet interface 305 which transmits the data block to the second line termination board 203 in one are more Ethernet messages.
It will be appreciated that the data block processor 307 may use any suitable algorithm for combining or ordering the data. In a simple example, the combined data may simply be ordered to start with all the appropriate data of a first E1 line, followed by all the appropriate data of a second E1 line etc. Within each E1 line group, the data may simply be arranged in the order of the time slots in which the data was received. In such an example, no additional overhead data is required and specific data can be identified simply by its position within this data block.
The first line termination board 201 furthermore comprises a mapping processor 309 which is coupled to the data block processor 307 and the Ethernet interface 305. The mapping processor 309 maps the data of the data block to output timeslots of the second line termination board 203. In an example where each input/output time slot comprises only a single data value, the mapping data may for example indicate that the first data value of the data block should be switched to time slot number five on the second E1 line of the second line termination board 203, the second data value should be switched to time slot number ten on the first E1 line, the third data value should be switched to time slot number 1 on the first E1 line etc.
The mapping data is fed from the mapping processor 309 to the Ethernet interface 305 which transmits it to the second line termination board 203 in one of more Ethernet messages.
It will be appreciated that the mapping processor 309 may use any suitable algorithm or approach to determine the mapping data. Specifically, the mapping data can be determined in response to connection information which defines which input connections/timeslots should be switched to which output connections/timeslots.
In the specific example, the connection information is received from the switch controller 211. For example, when a new connection is set up between two remote stations, the switch controller 211 receives information of the setup from the system and identifies the appropriate time slots, E1 lines and line termination boards involved in the call setup. For example, for a call setup between the first remote station 101 and the third remote station 115, the switch controller 211 may identify that call data from the first remote station 101 is received in time slot number 15 of E1 line 1 coupled to the first line termination board 201 and transmitted to the third remote station in time slot number three of E1 line 2 coupled to the second line termination board 203. Accordingly, it may send connection information to the first line termination board 201 informing it that E1 line 1, time slot number fifteen should be included in the data block sent to the second line termination board 203 where it should be allocated to time slot number three of E1 line 2.
When determining the mapping data for the second line termination board 203, the mapping processor 309 accordingly proceeds to determine the position of the data value of time slot number fifteen of E1 line 1 in the block of data. For this position, the mapping data corresponding to time slot number three of E1 line to is included in the mapping data.
The second line termination board 203 comprises an E1 interface 401 which interfaces to the E1 line from the second BSC 111. The second line termination board 203 furthermore comprises an Ethernet interface 403 which interfaces to the Ethernet network 209. The Ethernet interface 403 is coupled to a data block buffer 405 which is fed the data block when it is received from the first line termination board 201. The Ethernet interface 403 and the data block buffer 405 is furthermore coupled to a de-mapping processor 407 which allocates data of the data block to the output timeslots in response to the mapping data.
For example, the de-mapping processor 407 evaluates the mapping data and identifies that the data value in a specific position of the block of data should be included in time slot number three of E1 line 1. It accordingly proceeds to extract the relevant data value and to include this in the specific time slot.
The data of the data block may relate to more than one output connection. For example, the data of a second time slot of the first E1 line of the first line termination board 201 may need to be forwarded to a time slot of the second E1 line of the second line termination board 203. Accordingly, the mapping data may indicate that the data value at another location of the data block must be allocated to the identified time slot on the second E1 line of the second line termination board 203.
Thus, the switch 117 provides an efficient switching performance wherein data of any input connection can be switched to any other connection without requiring the use of the real-time connection switch matrix. It will be appreciated that improved performance can be achieved in many embodiments by having a switch interval that includes a larger number of input timeslots/connections. Specifically, the data buffer 303 may in many embodiments store more than ten input connections and in the specific example will store more than ten timeslots. Indeed in some embodiments, a significantly larger number of timeslots may be processed within each switch interval, such as for example a hundred or a thousand timeslots of each E1 line may be processed within each switch interval. This may allow improved trunking efficiency within the switch 117.
It will also be appreciated that a significant advantage of the described approach is that the mapping data and the in-call data may be communicated independently on the Ethernet network 209. This may for example allow the mapping data update to be independent of the switching interval. Specifically it may allow that the same mapping data is used for a plurality of switch intervals. For example, the required switching may only change when a new connection between remote stations is set up or terminated and the mapping data may be maintained constant between such events. Furthermore, in some embodiments only relative mapping data may be transmitted such as mapping data reflecting connection changes.
Specifically, switching updates do not have to be on a 125 us interval, but can be on an N×125 us interval as well up to, for example, five×125 us intervals. This may add a delay to call setup but this will generally be a negligible and deterministic delay.
Thus, in the system, signalling is decoupled from data transfer such that line termination board mapping, switch updating and data transferring are not directly dependent but can operate on different time scales providing a flexible architecture where, for instance, if a setup can wait for 50 ms at the expense of more connections being switched and more data being sent per unit time, then e.g. 100 ms switch update but 125 us data forward update can be implemented. That is, priority can be given to data switching as opposed to control processing. However, this does not preclude the inclusion of control information in data frames (control traffic could be time-synchronized with timeslot traffic and be sent using a common frame).
The described approach allows that data is packet routed over a fabric interconnect rather than a bus allowing facilitated packet signalling and data messaging. Furthermore, a common media is used for control and data (timeslots) traffic. In the system, switching control is performed in batches of line termination board to line termination board mappings of connections on a regular time interval (Epoch) rather than one connection at time, but can also be on a per connection basis if this preferred. Specifically, connection changes for a specific line termination board can be batched to form a connection request packet thereby reducing processing overhead.
Furthermore, the packet switch fabric approach can allow efficient scaling of the switch. For example, scaling from one fabric to multiple fabrics-size by providing the inter fabric connections that allow line termination boards from one fabric to set up connections to another line termination board on another fabric thereby providing extensibility for the switching and data planes.
The switch may furthermore be suitable for sub-rate switching. E.g. the mapping data can include a data rate indication for data for a given remote station and this can be used to allocate data to the individual output time slots. For example signalled line termination board mappings can describe the data block content of all connections carried in each data block between the line termination boards. Thus, no overhead is required to indicate e.g. 1, 2, 4, 8 bits of data per timeslot sent between line termination boards of the data block as this can be known by position and the indicated sub-rate in the mapping data.
The described architecture may furthermore allow a low complexity 1:N fan-out. For example, data from the first remote station 101 may be forwarded to a plurality of remote stations simply by including mapping data that maps the corresponding data of a data block to a plurality of output time slots/E1 lines. Furthermore, the input data can be included in data blocks for a plurality of line termination boards and the corresponding mapping data can be included in the mapping data for these line termination boards.
Also, the approach allows that only valid user data is forwarded to the destination. For example, due to discontinuous transmission techniques, such as DTX for GSM, some input time slots may not carry any data. In such a case, the data block processor 307 may not include data in the data block for these time slots. This may allow a massive saving on data routed at the switch fabric as data is only sent when there is anything to send on any of the connections at each frame interval at the interfaces.
It will be appreciated that the above description for clarity has described embodiments of the invention with reference to different functional units and processors. However, it will be apparent that any suitable distribution of functionality between different functional units or processors may be used without detracting from the invention. For example, functionality illustrated to be performed by separate processors or controllers may be performed by the same processor or controllers. Hence, references to specific functional units are only to be seen as references to suitable means for providing the described functionality rather than indicative of a strict logical or physical structure or organization.
The invention can be implemented in any suitable form including hardware, software, firmware or any combination of these. The invention may optionally be implemented at least partly as computer software running on one or more data processors and/or digital signal processors. The elements and components of an embodiment of the invention may be physically, functionally and logically implemented in any suitable way. Indeed the functionality may be implemented in a unit, in a plurality of units or as part of other functional units. As such, the invention may be implemented in a unit or may be physically and functionally distributed between different units and processors.
Although the present invention has been described in connection with some embodiments, it is not intended to be limited to the specific form set forth herein. Rather, the scope of the present invention is limited only by the accompanying claims. Additionally, although a feature may appear to be described in connection with particular embodiments, one skilled in the art would recognize that various features of the described embodiments may be combined in accordance with the invention. In the claims, the term comprising does not exclude the presence of other elements or steps.
Furthermore, although individually listed, a plurality of means, elements or method steps may be implemented by e.g. a unit or processor. Additionally, although individual features may be included in different claims, these may possibly be advantageously combined, and the inclusion in different claims does not imply that a combination of features is not feasible and/or advantageous. Also the inclusion of a feature in one category of claims does not imply a limitation to this category but rather indicates that the feature is equally applicable to other claim categories as appropriate. Furthermore, the order of features in the claims does not imply any specific order in which the features must be worked and in particular the order of individual steps in a method claim does not imply that the steps must be performed in this order. Rather, the steps may be performed in any suitable order.
