I. Field of the Invention
The invention relates to liquid crystal displays (LCDs). More specifically, the invention describes a method and apparatus for automatically determining a horizontal resolution and associated pixel clock rate.
II. Description of the Related Art
Digital display devices generally include a display screen including a number of horizontal lines. The number of horizontal and vertical lines defines the resolution of the corresponding digital display device. Resolutions of typical screens available in the market place include 640×480, 1024×768 etc. At least for the desk-top and laptop applications, there is a demand for increasingly bigger size display screens. Accordingly, the number of horizontal display lines and the number of pixels within each horizontal line has also been generally increasing.
In order to display a source image on a display screen, each source image is transmitted as a sequence of frames each of which includes a number of horizontal scan lines. Typically, a time reference signal is provided in order to divide the analog signal into horizontal scan lines and frames. In the VGA/SVGA environments, for example, the reference signals include a VSYNC signal and an HSYNC signal where the VSYNC signal indicates the beginning of a frame and the HSYNC signal indicates the beginning of a next source scan line. Therefore, in order to display a source image, the source image is divided into a number of points and each point is displayed on a pixel in such a way that point can be represented as a pixel data element. Display signals for each pixel on the display may be generated using the corresponding display data element.
However, in some cases, the source image may be received in the form of an analog signal. Thus, the analog data needs to be converted into pixel data for display on a digital display screen. In order to convert the source image received in analog signal form to pixel data suitable for display on a digital display device, each horizontal scan line must be converted to a number of pixel data. For such a conversion, each horizontal scan line of analog data is sampled a predetermined number of times (HTOTAL) using a sampling clock signal (i.e., pixel clock). That is, the horizontal scan line is usually sampled during each cycle of the sampling clock. Accordingly, the sampling clock is designed to have a frequency such that the display portion of each horizontal scan line is sampled a desired number of times (HTOTAL) that corresponds to the number of pixels on each horizontal display line of the display screen.
In general, a digital display unit needs to sample a received analog display signal to recover the pixel data elements from which the display signal was generated. For accurate recovery, the number of samples taken in each horizontal line needs to equal HTOTAL. If the number of samples taken is not equal to HTOTAL, the sampling may be inaccurate and resulting in any number and type of display artifacts (such as moire patterns).
Therefore what is desired is an efficient method and apparatus for determining a horizontal resolution of an analog video signal suitable for display on a fixed position pixel display such as an LCD.
According to the present invention, methods, apparatus, and systems are disclosed for determining a horizontal resolution of an analog video signal suitable for display on a fixed position pixel display such as an LCD.
In one embodiment, an apparatus for synchronizing an analog video signal formed of a plurality of associated video frames to a digital image formed of a plurality of pixels displayed on a digital display unit is described. The apparatus includes means for determining a synchronizing horizontal resolution (Htotal) that includes and means for finding a plurality of features for a selected one of a range of Htotal. The apparatus also includes means for tracking each of the plurality of features for each of the range of Htotal, means for measuring a transition zone for each of the plurality of found features for each of the range of Htotal, and means for determining the narrowest transition zone of the plurality of transition zones. The apparatus further includes means for associating a particular one of the range of Htotal corresponding to the narrowest transition zone to the synchronizing horizontal resolution and means for determining a synchronizing phase coupled to the means for determining the synchronizing horizontal resolution that includes, means for selecting an estimated phase based upon the synchronizing horizontal resolution, means for determining a flat region of a video signal corresponding to a selected found feature, and means for selecting the synchronizing phase based upon the flat region.
In another embodiment, a method of synchronizing an analog video signal formed of a plurality of associated video frames to a digital image formed of a plurality of pixels displayed on a digital display unit is described. A synchronizing horizontal resolution (Htotal) is determined by finding a plurality of features for a selected one of a range of Htotal. Next, each of the plurality of features is tracked for each of the range of Htotal and a transition zone is measured for each of the plurality of found features for each of the range of Htotal. Next, the narrowest transition zone of the plurality of transition zones is determined and then a particular one of the range of Htotal corresponding to the narrowest transition zone is associated with the synchronizing horizontal resolution. After the horizontal resolution is determined, a synchronizing phase is determined by selecting an estimated phase based upon the synchronizing horizontal resolution after which a flat region of a video signal corresponding to a selected found feature is determined. The synchronizing phase is determined based upon the flat region.
In yet another embodiment of the invention, a system for synchronizing an analog video signal formed of a plurality of associated video frames to a digital image formed of a plurality of pixels displayed on a digital display unit is described. The system includes a video signal evaluator arranged to provide an estimate of the synchronizing resolution, a feature finder unit arranged to find a feature, if any, associated with a pseudo-randomly selected pixel, a transition zone generator unit coupled to the feature finder unit arranged to generate a transition zone associated with the found feature based upon the estimated synchronizing resolution, and a minimum transition zone evaluator unit coupled to the transition zone detector for evaluating a minimum transition zone corresponding to the synchronizing resolution.
The invention will be better understood by reference to the following description taken in conjunction with the accompanying drawings.
Reference will now be made in detail to a particular embodiment of the invention an example of which is illustrated in the accompanying drawings. While the invention will be described in conjunction with the particular embodiment, it will be understood that it is not intended to limit the invention to the described embodiment. To the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.
In one embodiment, a method for determining a horizontal resolution (HTOTAL) is described. Each of a succession of associated video frames are surveyed for a number of displayed features based upon a pseudo-random selection of regions into which the displayed video frame is divided. During successive associated video frames, a minimum number of features is determined based upon a pre-selected number of scans. Subsequent to the determination of the minimum number of features, a transition region for each of plurality of horizontal resolution values (HTOTAL) is determined. Based upon a minimum transition zone, an associated HTOTAL is provided.
The invention will now be described in terms of an analog video signal synchronizer unit capable of providing a horizontal resolution (HTOTAL) and a pixel clock Pφ and methods thereof capable of being incorporated in an integrated semiconductor device well known to those skilled in the art. It should be noted, however, that the described embodiments are for illustrative purposes only and should not be construed as limiting either the scope or intent of the invention.
Accordingly,
In the described embodiment, the analog video signal synthesizer unit 200 includes a horizontal resolution estimator 206 arranged to provide a horizontal resolution value (HTOTAL) corresponding to the video signal 204 as well as a pixel clock phase based, in part, upon HTOTAL as well as the video signal 204. The synthesizer unit 200 includes a feature finder 208 arranged to detect a feature 210 within an active display region 212 of the LCD 202. Once the feature finder 208 has detected, or found, the feature 210, the coordinates of the found feature 210 are stored in a found feature location array 214 coupled to the feature finder unit 208. Once all the coordinates of all the found features 210 are stored in the array 214, a transition zone detector 216 detects a number of transition zones described below that are subsequently stored in a transition zone array 218 coupled thereto. A narrowest transition zone detector 220 coupled to the transition zone array 218 detects a narrowest transition zone that corresponds to a correct horizontal resolution HTOTAL.
Once HTOTAL has been determined by the horizontal resolution estimator 206, a pixel clock phase estimator 222 coupled thereto provides a best estimate of a pixel clock phase (Ø) based in part upon HTOTAL and the video signal 204. In the described embodiment, the pixel clock phase estimator 222 uses HTOTAL to provide a first estimate PØ1 of the pixel clock phase PØ which is used as a initial condition for scanning a flat region of the video signal 204 in order to confirm the validity (or not) of the first estimate PØ1 as the best estimate of the pixel clock phase PØ. In this way, the analog video signal synchronizer unit 200 is capable of providing both HTOTAL and the pixel clock phase PØ most consistent with the analog video signal 204 thereby providing the best “fit” of the image associated with the analog video signal 204 to the LCD 202. In those cases where the first estimate PØ1 is not the best fit, a second estimate PØ2 is generated, and so on, until a best fit of the image is obtained.
The following discussion describes operation of the analog video signal synchronizer unit 200 in accordance with a particular implementation of the invention. It should be noted, however, that the described operation is only one possible implementation and should therefore not be considered to be limiting either the scope or intent of the invention.
In operation, the feature finder 208 begins a feature search by pseudo-randomly selecting a number of pixels included in a first video frame 302 that are displayed in the active area display 212 as shown in
In the described embodiment, the feature finder 208 then stores for each first pixel in each region (such as, for example, pixel P1 of the region 304a) an associated first pixel video signal value P1val in, for example, a register (not shown) or other such data latch. Using the region 304a as an example, during a subsequent video frame 306, the feature finder 208 selects a second pixel coordinate (xi,y1) associated with a second pixel P2 as shown in
Edge=Abs{P1val}−Abs{P2val} equation 1.
If a value of Edge is positive, then the second pixel P2 corresponds to what is referred to as a rising edge type pixel associated with a rising edge feature. Conversely, if the value of Edge is negative, then the second pixel P2 corresponds to a falling edge pixel corresponding to a falling edge feature. It should be noted that at this point, all coordinates corresponding to all rising edge features and falling edge features so found are stored, respectively, in a rising edge array 308 and a falling edge array 310 as part of the found feature array 214. In some embodiments, the total number of found features are tallied and compared to a minimum number of found features. In some embodiments, this minimum number can be as low as four or as high as 10 depending on the situation at hand. This is done in order to optimize the ability to ascertain HTOTAL since too few found features can provide inconsistent results.
A more detailed example of the procedure followed by the feature finder 208 is further illustrated in
During a next scan (i.e., during a subsequent video frame) shown in
Once a predetermined number of scans has been completed (each of which corresponds to a different video frame), a determination is made whether or not a sufficient number of features have been found. It should be noted that once a feature is found and the corresponding region is marked as used, then that particular region is no longer subject to the pixel by pixel evaluation. In one embodiment, a minimum number of found features can be as low as four whereas a desired number of found features can be as many as ten or more. In this way, the likelihood of providing an accurate and reliable estimate of the horizontal resolution HTOTAL is substantially enhanced.
Although only the region 304a has been used in this example, it is well to note that the above describe procedure is performed substantially simultaneously on all the pseudo-randomly selected pixels Pa through Pm and their associated regions 304a through 304m.
Once the appropriate number of found features have been identified and their respective locations stored, a number of what are referred to as transition zones are measured by the transition zone detector 216. Since all features were created using the same pixel clock, when an estimated horizontal resolution HTOTAL is correct, then all features are aligned in such as way that when a pixel clock phase PØ is varied, the number of found features that appear to move together approaches the number of found features. For example, referring to
In the situation as shown in
Therefore, with reference to
Still referring to
Returning back to 1012, if it had been determined that the calculated difference is not great enough to indicate a feature, then control is passed directly to 1022 and at 1024, a determination is made whether or not the selected region is a last region. If the selected region is not a last region, then control is passed back to 1006, otherwise, a next frame is selected at 1026 and a next step is selected at 1028. At 1030, a determination is made whether or not the selected step is a last step, which if it is not, then control is passed to 1004, otherwise, a determination is made at 1032 whether or not the feature count is greater than or equal to a minimum feature count. If the feature count is not greater than or equal to the minimum feature count, then the process 1000 is aborted at 1034, otherwise, the process 1000 stops normally.
Returning to 1018, control is then passed to 1020 where a determination is made whether or not all features have been done. If all features have not been done, then control is passed back to 1208, otherwise, a next scan is done at 1022 while at 1024, a determination is made whether or not all scans have been done. If all scans have been done, then control is passed to 1206, otherwise, a determination is made at 1026 whether or not there are enough features. If there are not enough features, then the process 1200 aborts, otherwise the process 1200 stops normally.
At 1324, a determination is made whether or not all features have been done and if not, then control is passed directly to 1306, otherwise, a next phase is selected at 1326 followed by a determination at 1328 whether all phases have been done. If all phases have been done, then a smallest transition width is selected at 1330 which is associated with a best horizontal resolution, worst phase at 1332.
CPUs 1510 are also coupled to one or more input/output devices 890 that may include, but are not limited to, devices such as video monitors, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, or other well-known input devices such as, of course, other computers. Finally, CPUs 1510 optionally may be coupled to a computer or telecommunications network, e.g., an Internet network or an intranet network, using a network connection as shown generally at 895. With such a network connection, it is contemplated that the CPUs 1510 might receive information from the network, or might output information to the network in the course of performing the above-described method steps. Such information, which is often represented as a sequence of instructions to be executed using CPUs 1510, may be received from and outputted to the network, for example, in the form of a computer data signal embodied in a carrier wave. The above-described devices and materials will be familiar to those of skill in the computer hardware and software arts.
Graphics controller 1560 generates analog image data and a corresponding reference signal, and provides both to digital display unit 1570. The analog image data can be generated, for example, based on pixel data received from CPU 1510 or from an external encode (not shown). In one embodiment, the analog image data is provided in RGB format and the reference signal includes the VSYNC and HSYNC signals well known in the art. However, it should be understood that the present invention can be implemented with analog image, data and/or reference signals in other formats. For example, analog image data can include video signal data also with a corresponding time reference signal.
Although only a few embodiments of the present invention have been described, it should be understood that the present invention may be embodied in many other specific forms without departing from the spirit or the scope of the present invention. The present examples are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope of the appended claims along with their full scope of equivalents.
While this invention has been described in terms of a preferred embodiment, there are alterations, permutations, and equivalents that fall within the scope of this invention. It should also be noted that there are may alternative ways of implementing both the process and apparatus of the present invention. It is therefore intended that the invention be interpreted as including all such alterations, permutations, and equivalents as fall within the true spirit and scope of the present invention.
This application takes priority under 35 U.S.C. § 119 (e) of U.S. Provisional Patent Application No. 60/323,968 entitled “METHOD AND APPARATUS FOR SYNCHRONIZING AN ANALOG VIDEO SIGNAL TO AN LCD MONITOR” by Neal filed Sep. 20, 2001 which is incorporated by reference in its entirety for all purposes.
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