Frame buffered displays incorporate memory to store image data so that they can continue to refresh displayed image data without requiring an external data source. Such displays typically have two image data sources, one external to the display, such as video data supplied by an operating system executing on an external processor system, and the other supplied internally by a display controller or other logic. Because it has an internal image data source, a frame buffered display may permit selective gating or disabling of the external data source to save power. When the internally stored image data needs to be updated the external data source may be re-enabled to provide fresh image data to the display.
At the time that the external data source is re-enabled the internal data source and the external data source are likely to be out of synchronization. Standard display data sources or streams convey image data accompanied by two strobe signals: a vertical synchronization (Vsync) signal and a horizontal synchronization (Hsync) signal. The Vsync signal typically indicates when the display hardware should initiate or return to scanning the display data starting from the left-upper-most pixel of the display, while the Hsync signal typically indicates when the display hardware should begin scanning from the left-most pixel of each row of display pixels. When the two data sources are not synchronized the user may experience flickering or other display artifacts when the external data source is re-enabled because a significant interval or offset may exist between the Vsync signals of the two data sources.
The accompanying drawings, incorporated in and constituting a part of this specification, illustrate one or more implementations consistent with the principles of the invention and, together with the description of the invention, explain such implementations. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating the principles of the invention. In the drawings,
The following description refers to the accompanying drawings. Among the various drawings the same reference numbers may be used to identify the same or similar elements. While the following description provides a thorough understanding of the various aspects of the claimed invention by setting forth specific details such as particular structures, architectures, interfaces, techniques, etc., such details are provided for purposes of explanation and should not be viewed as limiting. Moreover, those of skill in the art will, in light of the present disclosure, appreciate that various aspects of the invention claimed may be practiced in other examples or implementations that depart from these specific details. At certain junctures in the following disclosure descriptions of well known devices, circuits, and methods have been omitted to avoid clouding the description of the present invention with unnecessary detail.
RX 102 may be any display interface receiver logic (e.g., red-green-blue complementary metal-oxide semiconductor (RGB CMOS), low voltage differential signaling (LVDS), unified display interface (UDI), etc.) capable of receiving external image data and/or display data and of transforming that data into a usable form. The invention is not, however, limited by how RX 102 receives and transforms display data. The output (Disp_ext) of RX 102 may include an externally generated vertical synchronization timing signal (Vsync_ext) in addition to image data and/or pixel data. Those skilled in the art will recognize that the externally generated display data received by RX 102 may also include additional signals such as a horizontal synchronization timing signal, a device enable signal etc. that are not particularly germane to the invention. As those skilled in the art may also recognize, the Vsync_ext signal received by RX 102 as part of Disp_ext may, in pass-thru mode, be used to coordinate when a display panel (not shown) associated with display controller system 100 begins displaying the image data and/or pixel data starting with, typically, the left-most pixel of the upper-most row of the display panel.
Timing controller 104 may be timing logic including any combination of hardware, software and/or firmware and may be capable, when system 100 is in self-refresh mode, of retrieving image data and/or pixel data from memory 112 using read FIFO 109 and memory controller 110 and of generating internal vertical synchronization (Vsync_int) and horizontal synchronization (Hsync_int) timing signals to be used in displaying that image data and/or pixel data. In accordance with some implementations of the invention and as will be explained in greater detail below, controller 104 may also be capable of adjusting blanking periods associated with the Vsync_int and Hsync_int in response to timing values (T_vals) provided by system controller 106. The uses and functionality of timing controller 104 will be explained in greater detail below.
System controller 106 may be system logic (i.e., control and/or processing logic) including any combination of hardware, software and/or firmware and may be capable in accordance with some implementations of the invention of assessing, when system 100 is in self-refresh mode, the degree of synchronization or temporal offset between the internal vertical synchronization (Vsync_int) and the external vertical synchronization (Vsync_ext) timing signals to determine appropriate timing values (T_vals) to be provided to timing controller 104. System controller 106 may further, in accordance with some implementations of the invention, be capable, in response to the degree of synchronization between Vsync_int and Vsync_ext, of controlling MUX 114 to provide image data and/or display data from either RX 102 or timing controller 104 to row and column driver logic (not shown). System controller 106 may also, in response to self_refresh_n signal supplied by a device such as a host processor (not shown) or an internal source, transition back to a self refresh mode where the internal vertical synchronization (Vsync_int) is provided with the display and/or image data. The uses and functionality of system controller 106 will be explained in greater detail below.
Memory 112 may comprise any memory device or mechanism suitable for storing and/or holding image data and/or pixel data (e.g., in the form of red-green-blue (RGB) color values). Memory 112 may, in some implementations of the invention, be described as a frame buffer that stores image data and/or pixel data and/or display data. While memory 112 may comprise any volatile or non-volatile memory technology such as Random Access Memory (RAM) memory or Flash memory, the invention is in no way limited by the type of memory employed for use as memory 112. The invention is also not limited to particular implementations of read and write FIFOs 108 and 109, memory controller 110 and/or MUX 114 and thus these items will not be described in greater detail herein.
Compute engine 206 may comprise, in accordance with some implementations of the invention, compute logic including any combination of hardware, software and/or firmware capable of determining synchronization timing values (T_vals) or the duration(s) of one or more blanking intervals in response to a count value provided by latch 204 and in response to existing timing values (Disp_int) and to an acceptable range of values and/or permissible timing ranges (T_rngs) provided by a timing controller, such as timing controller 104 of system 100. The uses and functionalities of compute engine 206 will be described in greater detail below.
Controller 200 also includes a comparator 208 that, in accordance with some implementations of the invention, may comprise any comparator logic capable of comparing the count value provided by latch 204 to a predetermined maximum count value or maximum offset value (Max_val). If the count value exceeds the maximum value then comparator 208 may provide a signal (e.g., MUX_sel) instructing, for example, MUX 114 of system 100 to select the image data and/or display data output (Disp_int) of timing controller 104. Alternatively, for example, if the count value does not exceed the maximum value then comparator 208 may provide a signal (e.g., a negated MUX_sel) instructing MUX 114 of system 100 to select the image data and/or display data output (Disp_ext) of RX 102. The uses and functionalities of comparator 208 will be described in greater detail below.
Vsync_int signal 402 includes a pulse 404 having a width 406 and two blanking intervals 408 and 410 defined, respectively, by the temporal offset or duration between pulse 406 and a last pixel of one frame of data signal 417 and a temporal offset or duration between pulse 406 and a first pixel of a next frame of data signal 417. Hsync_int signal 412 includes a pulse 414 having a width 416 and two blanking periods and/or blanking intervals 418 and 410 defined, respectively, by the temporal offset or duration between pulse 416 and a last pixel of one row of data signal 417 and a temporal offset or duration between pulse 416 and a first pixel of a next row of data signal 417. Although the invention is not limited by the term(s) used to describe intervals 408 and 410, those skilled in the art may recognize that blanking intervals 408 and 410 may be described, respectively, as a “front porch” and a “back porch” associated with pulse 404.
It should be noted, however, that in
Process 300 may begin with receiving an external vertical synchronization signal [act 302] and receiving an internal vertical synchronization signal [act 304]. In some implementations of the invention, acts 302 and 304 may, respectively, involve system controller 106 receiving signals Vsync_ext from RX 102 and Vsync_int from timing controller 104. Thus, referring to system controller 200 of
Process 300 may continue with determining the offset between the vertical synchronization signals [act 306]. In some implementations of the invention act 308 may be undertaken by counter 202 in conjunction with latch 204. As those skilled in the art will recognize, counter 202 and latch 204 may, in response to receiving respective signals Vsync_int and Vsync ext, provide to compute engine 206 and comparator 208 a signal proportional to the temporal offset or timing difference between Vsync_int and Vsync_ext. For example, the temporal offset may as be a count value produced by latch 204 where that count value is expressed in units of an internal pixel clock (Pclk). The invention is, however, not limited to using the logic shown in
Process 300 may then continue with a determination of whether the temporal offset exceeds a maximum value [act 308]. Act 308 may be implemented by having comparator 208 compare the temporal offset (e.g., count value) provided by latch 204 to a predetermined maximum acceptable offset value (e.g., Max_val) supplied to comparator 208. While the invention is not limited to particular maximum acceptable offset values, a variety of factors such as, for example, display resolution and pixel clock frequency may contribute to an appropriate maximum acceptable offset value. If the count value does not exceed the maximum value then process 300 may continue with switching from an internal image data and/or display data stream to an external image data and/or display data stream [act 309].
In some implementations of the invention, act 309 may be undertaken by MUX 114 in response to system controller 106 providing a signal MUX_sel instructing MUX 114 to switch from providing display driver logic (not shown) with an internal image data and/or display data stream (Disp_int) to providing that logic with an external image data and/or display data stream (Disp_ext). System controller 106 may instruct MUX 114 to do so because there may be no need to synchronize the external image data and/or display data stream (e.g., Disp_ext including Vsync_ext) to the internal image data and/or display data stream (e.g., Disp_int including Vsync_int) because the temporal offset between Vsync_ext and Vsync_int determined in 306 does not exceed a maximum acceptable offset.
If, on the other hand, the temporal offset (e.g., expressed as count value) exceeds the maximum value then process 300 may continue with the adjustment of internal vertical and/or horizontal timing values [act 310]. In some implementations of the invention act 310 may performed by system controller 106 in response to an indication that the external and internal vertical synchronization signals received, respectively, in acts 302 and 304 have a temporal offset determined in act 306 that has been found, in act 308, to meet or exceed a maximum acceptable value. Thus, referring again to system controller 200 of
Referring also to
Compute engine 206 may then adjust the values for the pulse widths 404 and 414 and/or the durations of one or more of blanking intervals 408, 410, 418 and 420 in response to the internal image data and/or display data and in response to a permissible timing signal (e.g., T_rngs) instructing engine 206 as to acceptable ranges of timing values for pulse widths 404 and 414 and/or blanking intervals 408, 410, 418 and 420. In doing so, engine 206 may, in undertaking act 310, generate an indicator or signal, T_vals, instructing timing controller 104 to modify the values of pulse widths 404 and 414 and blanking intervals 408, 410, 418 and 420 so that the internal vertical synchronization signal (Vsync_int) of Disp_int has a modified temporal offset with respect to the external vertical synchronization signal (Vsync_ext).
Thus, if a temporal offset 436 as measured exceeds a maximum acceptable value 434 for that temporal offset, then act 310 may involve adjusting timing periods, durations or intervals associated with the internal image data and/or display data or stream. One way this may be done is to have engine 206 and/or timing controller 104 add or subtract one or more blank pixels from a pixel data signal (e.g., P_data signal 417). While the invention is not limited to particular values of the permissible timing signal, a variety of factors such as, for example, the nature of a display's row and column drivers and physical characteristics of a given display may contribute to acceptable ranges of timing values as indicated by T_rngs.
Process 300 may then return to another iteration of determination of the temporal offset [act 306] associated with the Disp_int modified in act 310 and the assessment as to whether that offset exceeds the maximum value [act 308]. If the adjustment(s) made in a first iteration of act 310 were sufficient, that is, if the adjustment(s) of act 310 have reduced the temporal offset between the internal and external vertical synchronization signals such that the offset does not exceed the maximum allowable value then process 300 may terminate. If, however, the adjustment(s) made in a first iteration of act 310 were not sufficient, that is, if the adjustment(s) of act 310 have not reduced the temporal offset between the internal and external vertical synchronization signals such that the offset does not exceed the maximum allowable value then process 300 may continue with another iteration of act 310 followed by acts 306 and 308.
Thus, in accordance with some implementations of the invention, acts 306-310 may repeat as many times as necessary until such time as the measured temporal offset is less than or equal to the maximum allowable value. Until a the measured offset is less than or equal to the maximum allowable value system controller 106 may use comparator 208 to provide a signal MUX_sel to MUX 114 instructing the MUX to continue providing the internal image data and/or display data (e.g., Disp_int including Vsync_int) to the display driver logic (not shown).
The acts shown in
System 500 may assume a variety of physical implementations. For example, system 500 may be implemented in a personal computer (PC), a networked PC, a server computing system, a handheld computing platform (e.g., a personal digital assistant (PDA)), a gaming system (portable or otherwise), a 3D capable cellular telephone handset, etc. Moreover, while all components of system 500 may be implemented within a single device, such as a system-on-a-chip (SOC) integrated circuit (IC), components of system 500 may also be distributed across multiple ICs or devices. For example, host processor 502 along with components 506, 512, and 514 may be implemented as multiple ICs contained within a single PC while graphics processor 504 and components 508 and 516 may be implemented in a separate device such as display 518 coupled to host processor 502 and components 506, 512, and 514 through communications pathway 510.
Host processor 502 may comprise a special purpose or a general purpose processor including any control and/or processing logic, hardware, software and/or firmware, capable of providing graphics processor 504 or display processor 516 with image data and/or associated instructions. In one implementation, host processor 502 may be capable of performing any of a number of tasks that support synchronizing of asynchronous display streams. These tasks may include, for example, although the invention is not limited in this regard, providing logic in display processor 516 and/or display 518 with maximum temporal offset values (e.g., Max_val) and/or permissible timing value ranges (i.e., T_rngs), downloading microcode (via antenna 515 and interfaces 514) to processors 504 and/or 516, initializing and/or configuring registers within processors 504 and/or 516, interrupt servicing, and providing a bus interface for uploading and/or downloading image data, etc. In alternate implementations, some or all of these functions may be performed by graphics processor 504 and/or display processor 516. While FIG. 5 shows display processor 516 and display 518 as distinct components, the invention is not limited in this regard and those of skill in the art will recognize that processor 516 possibly in addition to other components of system 500 may be implemented within display 518.
Bus or communications pathway(s) 510 may comprise any mechanism for conveying information (e.g., graphics data, instructions, etc.) between or amongst any of the elements of system 500. For example, although the invention is not limited in this regard, communications pathway(s) 510 may comprise a multipurpose bus capable of conveying, for example, instructions (e.g., macrocode) between processor 502 and processors 504 or 516. Alternatively, pathway(s) 510 may comprise a wireless communications pathway.
Display panel 518 may be any display device, such as a frame buffered display panel, capable of displaying both internally and externally generated image data and/or display data or streams. Further, in accordance with some implementations of the invention, display panel 518 may include logic similar to that described above with respect to systems 100 and/or 200 and at least capable of performing process 300 as described above. In some implementations of the invention display panel 518 may be a liquid crystal display (LCD) panel. The invention is, however, not limited to a specific type of display technology and, thus, display panel 518 may be, for example, a plasma display panel (PDP).
Display processor 516 may comprise any processing logic, hardware, software, and/or firmware, capable of converting rasterized image data supplied by graphics processor 504 into a format suitable for driving a display (i.e., display-specific data). For example, while the invention is not limited in this regard, processor 504 may provide image data to processor 516 in a specific color data format, for example in a compressed red-green-blue (RGB) format, and processor 516 may process such RGB data by generating, for example, corresponding LCD drive data levels etc. Although
Thus, in accordance with some implementations of the invention, a frame buffered display timing controller may provide for the synchronization of asynchronous display streams by adjusting the horizontal and/or vertical blanking periods. In this manner several blank pixels and/or lines of blank pixels may be added or subtracted to change the amount of time it takes to transmit a frame of image data. Thus, a state machine in accordance with some implementations of the invention can monitor the vertical synchronous pulse associated with an externally generated display stream and the temporal or phase offset of that pulse with respect to an internally generated vertical synchronous pulse and may instruct the logic that generated the internal vertical synchronous pulse to shorten or lengthen vertical and/or horizontal blanking periods in order to reduce the temporal or phase offset to an acceptable value. In this manner, asynchronous display streams may be synchronized so as to avoid undesirable visual artifacts and/or damage to the display structure that may result from transitioning between asynchronous display streams.
While the foregoing description of one or more instantiations consistent with the claimed invention provides illustration and description of the invention it is not intended to be exhaustive or to limit the scope of the invention to the particular implementations disclosed. Clearly, modifications and variations are possible in light of the above teachings or may be acquired from practice of various implementations of the invention. Clearly, many other implementations may be employed to provide for the synchronization of asynchronous display streams consistent with the claimed invention.
No device, element, act, data type, instruction etc. set forth in the description of the present application should be construed as critical or essential to the invention unless explicitly described as such. Also, as used herein, the article “a” is intended to include one or more items. Moreover, when terms or phrases such as “coupled” or “responsive” or “in communication with” are used herein or in the claims that follow, these terms are meant to be interpreted broadly. For example, the phrase “coupled to” may refer to being communicatively, electrically and/or operatively coupled as appropriate for the context in which the phrase is used. In addition, the terms “display data”, “image data” and “pixel data” have been used interchangeably throughout this specification. Variations and modifications may be made to the above-described implementation(s) of the claimed invention without departing substantially from the spirit and principles of the invention. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.
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