Patent Application
20070242156
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
To provide a better understanding to anyone who is familiar with the technical aspect in this area, please first refer to
Next, the received image source signal is translated from a first format into a second format at the first clock (step 103). In practice, the controlling of the input element using the first clock signal can be used to control to output of the received image source signal through a delay so that the translation of the image source signal from the first format to the second format is achieved. Furthermore, according to the adjusted ratio of the image resolution, the translation format of the image source signal can be predetermined. When the image bit length per unit clock cycle of the image source signal in the first format is N bits, the image bit length per unit clock cycle of the image source signal in the second format is, for example, 2N bits. The two formats can have a multiple relation such as a positive whole number multiple relation.
Then, similarly, the second formatted image source signal is temporarily stored at the first clock (step 105). Next, in step 107, the temporarily stored data in the foregoing storage format is read out, that is, the image source signal in the second format is read out. Because, based on the control of the same first clock, the image bit length per unit clock cycle of the image source signal in the first format and that of the second format has a multiple relation, this implies that the data volume of the image source signal per unit clock cycle received in step 101 and the data volume of the image source signal per unit clock cycle read out in step 107 has a multiple relation. In other words, without providing extra clock signals, the data volume of the source image signal that can be read per unit clock cycle is increased through changing the format of the image source signal.
Then, the read-out image source signal in the second format is output (step 109). According to the quantity of data required in the image translation operation, whether to translate the image source signal in the second format into the image source signal in a third format can be determined before outputting the signal.
Finally, an image translation execution such as an insertion compensation algorithm is carried out on the output image source signal in the second format to obtain the target image signal (step 111). Because the data volume of the source image signal read out per unit clock cycle during the operation can be increased through changing the format of the source signal, therefore, based on the control of the same first clock, a shorter work cycle can be used to read out the data volume of the image source signal required by each operation and increase the operational efficiency under the same clock cycle. In other words, reading the image source signals multiple times in each fixed cycle is achieved.
In the present invention, the content of the second format and the third format of the image source signal can be adjusted according to the translation of the image resolution or the contraction/expansion ratio of the image. As an example, under the control of the first clock and the image bit length per unit clock cycle of the image source signal in the first format being N bits, where N is a positive whole number as an example; if the image resolution needs to increase twice, then the image bit length per unit clock cycle of the read-out image source signal in the second format in step 107 is 2N bits. Obviously, if the image bit length per unit clock cycle of the image source signal in the second format is smaller than 2N bits, then an image source signal having an image bit length per unit clock cycle of 2N bits can be provided through step 109 of translating the second format to the third format.
Furthermore, according to the spirit of the present invention, there is no need to fixedly translate the image source signal in the first format into the image source signal in the second format with an image bit length per unit clock cycle of 2N bits. The image source signal in the first format can be randomly translated into different formats as long as it can provide the image bit length per unit clock cycle required in an operation so that the image source signal can be read multiple times within the fixed cycle of operation.
Finally, through the foregoing results and under the control of the same first clock, an operation such as an insertion compensation algorithm on the image source signal in storage format read out in step 107 can be carried out to generate a target image signal (step 109). The target image signal can be used by the display of a computer, for example.
The output control element 221 is used for reading out the image source signal 213 of the second format from the buffer at the first clock from the buffer 211 according to the first clock CLK and through the outputting of a control signal 225. In addition, the output control element controls to output the image source signal of a third format through a second control signal at the first clock. the data volume of the image source signal 213 in the second format read out per unit clock cycle from the output control element 221 at the same first clock CLK and the data volume of the image source signal 203 in the first format received per unit clock cycle from the input control element 201 has a positive multiple relation, not necessarily a positive whole number relation.
To provide an image source signal 215 in a third format having an image bit length per unit clock cycle required by the operation, the output control element 221 translates the image source signal 214 in the second format read out from the buffer 211 into the image source signal 215 in the third format before outputting it.
Aside from the description in
The clock generator 341 produces a synchronous signal 343 for the target image signal 331. Under the control of the first clock CLK and according to the input synchronous signal 302, which comprises a horizontal synchronous signal and a vertical synchronous signal that accompany the image source signal 203, the synchronous signal 343 that comprises a horizontal synchronous signal and a vertical synchronous signal required by the display device 351 is produced.
When the image source signal 213 in the second format is written into the buffer 211, the input control element 201 slows down the output rate so that an image source signal 213 in the second format is output every two clock cycles. The image signal 213 in the second format includes two batches of data per unit clock cycle, and furthermore, each output includes two batches of data. Under these circumstances, the image source signal 213 in the second format can be stored in parallel. In other words, two batches of data can be stored in one address.
Therefore, within a horizontal synchronous signal cycle of inputting the image source signal 203 in the first format into the input control element 201, two output horizontal synchronous signals can be read from the buffer 211 in synchrony with the image source signal 213 in the second format. More simply, within the input horizontal synchronous signal cycle, the data data1˜data14 within a horizontal image line can be read twice.
For the interpolation algorithm circuit 331 in
In summary, the present invention provides a synchronous image translation method and apparatus such that, under the control of a single clock and through the control of the image source signal by the input control element, the image source signal in different formats are written into the buffer, the storage format of the image source signal is determined, and the storage format formatted image sources signal is output by controlling the output element to achieve the purpose of a synchronous image translation. In the present invention, the same clock is used before and after the format of the image source signal is translated and written into the buffer and read out of the buffer. Therefore, the image bit length per unit clock cycle after translating the image sources signal is immediately changed. That is, after the operation terminal has accessed the format translated image source signal, the image data volume accessed per unit clock cycle can be increased to improve the resolution of accessing the image source signal during the operation. The synchronous image translation apparatus in the present invention also simplifies the design of the image translation product and reduces the production cost. Furthermore, the image translation product needs no extra apparatus and hence consumes no extra power. Thus, the synchronous image translation apparatus can be manufactured at a price level comparable to other products in the market.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 95112966 | Apr 2006 | TW | national |
