The present invention relates to flat panel displays, specifically to feedback systems for stabilizing emissions of flat panel displays.
Nuelight Corporation, the assignee of the present invention, has many pending patent applications that disclose emission stabilization techniques for emissive flat panel displays. The patent application numbers are U.S. Pat. Nos. 11/016357, 11/016137, 11/016686, 11/016164, 11/0156638 and 11/016372, and they are incorporated herein by reference. These applications disclose optical sensor feedback systems that compensate for the thin film transistor (TFT) drift and the aging characteristics of organic light emitting diodes (OLED). The OLED technology is being developed and implemented in new flat panel displays.
The horizontal line enable conductor 40 (labeled Row N select) to is used to enable the downloading of the data voltage to drive the current source (TFT T1) for the OLED D1, and to simultaneously activate the TFT T3 of the sensor circuit 30. Conductor line 40 is connected to the gates of T1 and T3. Line 40 supplies enabling voltages to the gates of both T1 and T3. When both T1 and T3 are activated, the sensor line 50, which is coupled to the sensor circuit 30, is first read by a sensor reader circuit and then the data voltage is downloaded to the OLED current source T1, C1 and T2 by using the conductor column driver line 60 coupled to the driver circuit 20.
The row address time, which is the amount of time for which conductor line 40 activates T1 and T3, is used to perform two operations, in which the sensor S1 is first read out and then the new voltage data is down loaded to the driver circuit 20. The time duration of the row address is determined by the frame rate and the number of lines (or rows) of pixel circuitry on the display. Thus, for a 1000 line display running at 60 frames per second (fps), the row address time is 16.67 microseconds less the horizontal retrace time. The horizontal retrace time is the time between the ending of the writing of data to one row to the beginning of the writing of data to the next row. The horizontal retrace time can be 5 to 10 microseconds leaving only 6.67 to 11.67 microseconds to do both sensor reading and voltage data down loading.
The arrangement of
The present invention discloses a display having a first linear array of light emitting elements and a second linear array of light emitting elements. A first sensor circuit is coupled to a light emitting element of the first linear array for detecting an output of the light emitting element of the first linear array. A second sensor circuit is coupled to a light emitting element of the second linear array for detecting an output of the light emitting element of the second linear array. A control circuit simultaneously causes the light emitting element of the first linear array to emit light and the sensor circuit coupled to the light emitting element of the second linear array to provide information corresponding to the detected output of the light emitting element of the second linear array to a sensor reader circuit.
The above and other objects and advantages of the present invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:
In
Note that in this embodiment the data download 84 from the column driver 60 to the data transistors T1 begins slightly after the retrace time begins. At the end of the retrace pulse 82 the gate enable pulse for Row N 86 begins and since the gate enable line 40 for Row N is also the gate enable line 40 for the sensor S1′ in Row N+1, the pulse for sensor enable Row N+1 88 begins at the same time.
Both gate enable pulses 86 and 88 end at the beginning of the next retrace pulse 82 for Row N+1. This process continues until the last row (line) in the display has been downloaded, as is shown by the timing waveforms 90, 92, 94, 96, 98 and 100. Note that the pulse for the gate enable for last row 98 corresponds with the sensor enable pulse for the top row 100, which is Row N. In one embodiment, an extra horizontal conducting line runs along the top of the display and accesses the gates of all the T3s in the first row. This line is coupled to a vertical line conductor running between this top sensor gate line and the bottom data gate line for the last row.
The present invention can be implemented in the following embodiments: active matrix backplanes using amorphous silicon as the channel semiconductor; active matrix backplanes using poly silicon as the channel semiconductor; active matrix backplanes using crystalline silicon as the channel semiconductor; active matrix backplanes employing a direct sensor measurement during the address time; active matrix backplanes employing an integration period for the sensor of one frame or a fraction of a frame or for several frames or for any number of frames; active matrix display using any emissive materials including OLEDs, EL devices, plasma, and electron beam activated phosphors or vacuum fluorescent displays; active matrix backplanes of any number of lines or columns; active matrix backplanes in any geometrical configuration including rectilinear and circular; active matrix backplanes on any substrate including metal, glass, plastic ridged or flexible; sensors using any optically active material including amorphous silicon, poly silicon, crystalline silicon, cadmium selenide, OLED material; sensors that are passive; sensors that are active; sensors in any circuit configuration; and displays employed in any use including computer monitors, entertainment systems, and any system requiring or using a device for visual graphics or read outs.
This application claims the benefit of U.S. Provisional Application No. 60/644,676, filed Jan. 12, 2005, which is incorporated herein by reference.
Number | Date | Country | |
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60644676 | Jan 2005 | US |