Patent Application
20240235592
This invention relates generally to wireless technology and more particularly to millimeter wave (mmwave) radio technology.
Data communication involves sending data from one device to another device via a communication medium (e.g., a wire, a trace, a twisted pair, a coaxial cable, air, etc.). The devices range from dies within an integrated circuit (IC), to ICs on a printed circuit board (PCB), to PCBs within a computer, to computers, to networks of computers, and so on.
Data is communicated via a wired and/or a wireless connection in accordance with a data communication protocol. Data communication protocols dictate how the data is to be formatted, encoded/decoded, transmitted, and received. For some data communications, digital data is modulated with an analog carrier signal and transmitted/received via a modulated radio frequency (RF) signal.
Wireless technologies based on relatively high radio frequencies have proven capable of delivering data transmissions in the range of multi-gigabits/second with relatively lower latency. In general, multi-gigabit/second communication speeds require relatively wide transmission bandwidths, which are available with high carrier frequency radio systems, such as frequencies in the millimeter wave (mmwave) range (i.e., 30-300 GHz). For example, a wireless data communication protocol such as IEEE 802.11ay dictates how wireless communications are to be done between local and metropolitan area networks, including defining multiple channels from 57 GHz to 71 GHz that provide, for example, potential coded data rates up to 35.4 Gbps when four channels are bonded together.
Radio systems designed for use in the mmwave range benefit from high levels of integration, allowing for manufacturing efficiencies that can lead to lower cost, shorter manufacturing periods and higher performance. As is further known, millimeter-wave radio systems necessarily require testing and/or calibration in order to meet expected performance requirements.
In an example, the system of
The method begins at step 100, with a DC supply being used to bias the third winding of a balanced to unbalanced (balun) transformer coupling the power amplifier (PA) and a low-noise amplifier (LNA) in a radio transmit/receive (TRX) front end, such as the TRX front end illustrated in
In an example, the loop back testing method of
In a specific example of implementation and operation, a method for testing a radio front-end comprises biasing a balun at a third winding, where a transmit power amplifier and a low noise amplifier are coupled to a secondary winding of the balun and the biasing causes the transmit power amplifier in a transmit path to partially activate to produce a power amplifier output. The method continues, by providing the power amplifier output to the low noise amplifier and measuring one or more signal path parameters of the radio front-end to produce one or more test results. The method continuers, by correlating the one or more test results to one or more predetermined test values; and in response to the correlating, determining whether the test results are favorable. In a specific example, the method includes activating a transmit/receive switch to bias the balun, where the transmit/receive switch is integrated on the radio front-end. In an example, a power amplifier, low-noise amplifier, transmit/receive switch and balun are integrated on a common integrated circuit.
In another specific example of implementation and operation, method for testing a radio front-end comprises biasing a balun at a third winding, where a transmit power amplifier and a low noise amplifier are coupled to a secondary winding of the balun and where the biasing causes the transmit power amplifier in the TX path to partially activate to produce a power amplifier output. The method continues by providing the power amplifier output to the low noise amplifier, and measuring one or more signal path parameters of the radio front-end to produce one or more test results. The method then continues by correlating the one or more test results to one or more predetermined test values to produce correlated test values and based on the correlated test values, determining whether the test results are favorable. In a specific related example, the method includes activating a transmit/receive switch to bias the balun, where the transmit/receive switch is integrated on the radio front-end. In another specific related example, the power amplifier, the low-noise amplifier, the transmit/receive switch and the balun are integrated on a common integrated circuit.
In an example, local oscillator feed-through (LOFT) and image rejection signals can be found in the transmit (TX) signal for a radio. The LOFT and/or image rejection signals can be removed and/or attenuated using an ADC, to convert the TX signal to digital for processing in the digital domain (using, for example, a fast Fourier transform function (FFT)), however, the ADC and processing consume power and can introduce latency to the TX signal. For example, an ADC can be implemented as a successive-approximation-register (SAR). In a related example, the SAR ADC mentioned is configured for low frequency conversion and can be used as a house-keeping ADC (HKADC) (sometimes referred to as an auxiliary ADC). In a specific example, a signal path ADC can be differentiated from a traditional SAR, due to, for example, due to its relatively high sample rate requirement(s).
In a quadrature-based RF transceiver, a local oscillator (LO) can leak to the output of the receiver, producing LO feedthrough. In an example, DC offset is multiplied with the local oscillator (LO) signal and can be a dominant contributor to LO Feedthrough “leakage”. Whereas leakage can be the result of capacitive coupling to the output, etc., in an example, DC offset can derive from a baseband signal being multiplied by LO coupling to the output. Additionally, quadrature-based RF transceiver with in-phase and quadrature (I/Q) components are known to exhibit imbalance (I/Q imbalance) between the two 90-degree quadrature signals, caused by, for example, non-ideal mixers, amplifier offsets and frequency error between transmit and receive channels etc. An amount of I/Q imbalance can be represented as I/Q Offset (also called I/Q origin offset), where the I/Q offset indicates the magnitude of a carrier feedthrough signal. Additionally, uncalibrated I/Q gain/offset can result in undesired sideband emissions in an associated transmitter. In most cases the response for a given transceiver can be calibrated so that the I/Q components will have substantially the same gain/offset.
In an example, calibration can be accomplished in the digital domain using an analog to digital converter (ADC). In another example, calibration can be done using readily available measuring equipment, such as an oscilloscope. In a specific example of implementation and operation, an envelope detector can be configured to measure the power output of a transceiver. In an example, the envelope detector can be used initially to measure a signal envelope at each of a plurality of power levels.
At step 402, the 50 MHz tone is upconverted and at step 404 the 60.05 GHz tone presents at the output of the power amplifier and the insertion of the 50 MHz tone will likewise result in an LO feedthrough tone at 60 GHz. In an example, in the time-domain the output of an example transceiver will be modulated with a 50 MHz sine wave, enabling an envelope detector at step 406 to extract the LO feedthrough tone. At step 408, if only one tone is measured at the input of the envelope detector the output will be representative of DC offset. At step 410 DC offset is determined based on the single tone.
In another specific example of implementation and operation, the Log Amplifier can be configured to provide an average DC out voltage for the LO feed through tone and the I/Q imbalance image as a function of sweeping the low frequency injection tone across a range of frequencies. In an example, the average DC out voltage from the Log Amplifier can be dependent on the filter response “shape”. In an example, the average DC out voltage from the Log Amplifier sweeping the low frequency injection tone across a range of frequencies will produce a peak that correlates to the peak of the low pass filter response. In a related example, the low pass filter response can exhibit a different peak position (at a lower or higher peak based on sweep frequency), however the relationship (correlation) of the low pass filter response peak will be substantially maintained once the LO feedthrough and I/Q imbalance are characterized in a given system.
In another specific example of implementation and operation, referring, for example, to
In some examples of implementation, the quality of rejection of an LO feedthrough tone used in a calibration process can depend on the quality of filter used in the calibration mechanism. For example, if a filter used in the implementation is insufficiently precise, a resultant LO feedthrough tone rejection/reduction will be affected adversely. In an example, if cut-off for a particular filter is at a frequency higher than an associated calibration tone (LOFT), a respective level of IQ tone rejection can be diminished. In another example, if a given filter is at a frequency lower than an associated calibration tone (LOFT), the residue level of a desired LO feedthrough tone selected for detection is reduced, once again the resultant calibration result will be respectively lower precision. Accordingly, in an example, when the frequency response of a select filter can be predetermined, the associated low frequency tone for calibrating LO feedthrough can be better adjusted to increase the efficiency of the associated filter response.
In a related example, an envelope detector can be adapted to operate more efficiently when the amplitude of the low frequency injection tone increases. In an example, as the low frequency injection tone increases, the amplitude of any higher order harmonics will also increase. Accordingly, if the low frequency injection tone amplitude is sufficiently high the I/Q imbalance image in bypass mode can include a second harmonic of the low frequency injection tone. In an example of implementation, a low frequency injection tone can be configured for programmability, so that when the calibration procedure is adapted for bypass mode the low frequency injection tone can be selected at frequency high enough that second (and higher) harmonics of the low frequency injection tone will not be problematic. In an alternative example of implementation and operation, when the calibration procedure is adapted for bypass mode the low frequency injection tone frequency can be divided in half, so that any harmonics are filtered out in the LO feed through process.
It is noted that terminologies as may be used herein such as bit stream, stream, signal sequence, etc. (or their equivalents) have been used interchangeably to describe digital information whose content corresponds to any of a number of desired types (e.g., data, video, speech, text, graphics, audio, etc. any of which may generally be referred to as ‘data’).
As may be used herein, the terms “substantially” and “approximately” provide industry-accepted tolerance for its corresponding term and/or relativity between items. For some industries, an industry-accepted tolerance is less than one percent and, for other industries, the industry-accepted tolerance is 10 percent or more. Other examples of industry-accepted tolerance range from less than one percent to fifty percent. Industry-accepted tolerances correspond to, but are not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, thermal noise, dimensions, signaling errors, dropped packets, temperatures, pressures, material compositions, and/or performance metrics. Within an industry, tolerance variances of accepted tolerances may be more or less than a percentage level (e.g., dimension tolerance of less than +/−1%). Some relativity between items may range from a difference of less than a percentage level to a few percent. Other relativity between items may range from a difference of a few percent to magnitude of differences.
As may also be used herein, the term(s) “configured to”, “operably coupled to”, “coupled to”, and/or “coupling” includes direct coupling between items and/or indirect coupling between items via an intervening item (e.g., an item includes, but is not limited to, a component, an element, a circuit, and/or a module) where, for an example of indirect coupling, the intervening item does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. As may further be used herein, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two items in the same manner as “coupled to”.
As may even further be used herein, the term “configured to”, “operable to”, “coupled to”, or “operably coupled to” indicates that an item includes one or more of power connections, input(s), output(s), etc., to perform, when activated, one or more its corresponding functions and may further include inferred coupling to one or more other items. As may still further be used herein, the term “associated with”, includes direct and/or indirect coupling of separate items and/or one item being embedded within another item.
As may be used herein, the term “compares favorably”, indicates that a comparison between two or more items, signals, etc., provides a desired relationship. For example, when the desired relationship is that signal 1 has a greater magnitude than signal 2, a favorable comparison may be achieved when the magnitude of signal 1 is greater than that of signal 2 or when the magnitude of signal 2 is less than that of signal 1. As may be used herein, the term “compares unfavorably”, indicates that a comparison between two or more items, signals, etc., fails to provide the desired relationship.
As may be used herein, one or more claims may include, in a specific form of this generic form, the phrase “at least one of a, b, and c” or of this generic form “at least one of a, b, or c”, with more or less elements than “a”, “b”, and “c”. In either phrasing, the phrases are to be interpreted identically. In particular, “at least one of a, b, and c” is equivalent to “at least one of a, b, or c” and shall mean a, b, and/or c. As an example, it means: “a” only, “b” only, “c” only, “a” and “b”, “a” and “c”, “b” and “c”, and/or “a”, “b”, and “c”.
As may also be used herein, the terms “processing module”, “processing circuit”, “processor”, “processing circuitry”, and/or “processing unit” may be a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on hard coding of the circuitry and/or operational instructions. The processing module, module, processing circuit, processing circuitry, and/or processing unit may be, or further include, memory and/or an integrated memory element, which may be a single memory device, a plurality of memory devices, and/or embedded circuitry of another processing module, module, processing circuit, processing circuitry, and/or processing unit. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. Note that if the processing module, module, processing circuit, processing circuitry, and/or processing unit includes more than one processing device, the processing devices may be centrally located (e.g., directly coupled together via a wired and/or wireless bus structure) or may be distributedly located (e.g., cloud computing via indirect coupling via a local area network and/or a wide area network). Further note that if the processing module, module, processing circuit, processing circuitry and/or processing unit implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory and/or memory element storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. Still further note that, the memory element may store, and the processing module, module, processing circuit, processing circuitry and/or processing unit executes, hard coded and/or operational instructions corresponding to at least some of the steps and/or functions illustrated in one or more of the Figures. Such a memory device or memory element can be included in an article of manufacture.
One or more examples have been described above with the aid of method steps illustrating the performance of specified functions and relationships thereof. The boundaries and sequence of these functional building blocks and method steps have been arbitrarily defined herein for convenience of description. Alternate boundaries and sequences can be defined so long as the specified functions and relationships are appropriately performed. Any such alternate boundaries or sequences are thus within the scope and spirit of the claims. Further, the boundaries of these functional building blocks have been arbitrarily defined for convenience of description. Alternate boundaries could be defined as long as the certain significant functions are appropriately performed. Similarly, flow diagram blocks may also have been arbitrarily defined herein to illustrate certain significant functionality.
To the extent used, the flow diagram block boundaries and sequence could have been defined otherwise and still perform the certain significant functionality. Such alternate definitions of both functional building blocks and flow diagram blocks and sequences are thus within the scope and spirit of the claims. One of average skill in the art will also recognize that the functional building blocks, and other illustrative blocks, modules and components herein, can be implemented as illustrated or by discrete components, application specific integrated circuits, processors executing appropriate software and the like or any combination thereof.
In addition, a flow diagram may include a “start” and/or “continue” indication. The “start” and “continue” indications reflect that the steps presented can optionally be incorporated in or otherwise used in conjunction with one or more other routines. In addition, a flow diagram may include an “end” and/or “continue” indication. The “end” and/or “continue” indications reflect that the steps presented can end as described and shown or optionally be incorporated in or otherwise used in conjunction with one or more other routines. In this context, “start” indicates the beginning of the first step presented and may be preceded by other activities not specifically shown. Further, the “continue” indication reflects that the steps presented may be performed multiple times and/or may be succeeded by other activities not specifically shown. Further, while a flow diagram indicates a particular ordering of steps, other orderings are likewise possible provided that the principles of causality are maintained.
The one or more examples are used herein to illustrate one or more aspects, one or more features, one or more concepts, and/or one or more examples. A physical example of an apparatus, an article of manufacture, a machine, and/or of a process may include one or more of the aspects, features, concepts, examples, etc. described with reference to one or more of the examples discussed herein. Further, from figure to figure, the examples may incorporate the same or similarly named functions, steps, modules, etc. that may use the same or different reference numbers and, as such, the functions, steps, modules, etc. may be the same or similar functions, steps, modules, etc. or different ones.
Unless specifically stated to the contra, signals to, from, and/or between elements in a figure of any of the figures presented herein may be analog or digital, continuous time or discrete time, and single-ended or differential. For instance, if a signal path is shown as a single-ended path, it also represents a differential signal path. Similarly, if a signal path is shown as a differential path, it also represents a single-ended signal path. While one or more particular architectures are described herein, other architectures can likewise be implemented that use one or more data buses not expressly shown, direct connectivity between elements, and/or indirect coupling between other elements as recognized by one of average skill in the art.
The term “module” is used in the description of one or more of the examples. A module implements one or more functions via a device such as a processor or other processing device or other hardware that may include or operate in association with a memory that stores operational instructions. A module may operate independently and/or in conjunction with software and/or firmware. As also used herein, a module may contain one or more sub-modules, each of which may be one or more modules.
As may further be used herein, a computer readable memory includes one or more memory elements. A memory element may be a separate memory device, multiple memory devices, or a set of memory locations within a memory device. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. The memory device may be in a form a solid-state memory, a hard drive memory, cloud memory, thumb drive, server memory, computing device memory, and/or other physical medium for storing digital information.
While particular combinations of various functions and features of the one or more examples have been expressly described herein, other combinations of these features and functions are likewise possible. The present disclosure is not limited by the particular examples disclosed herein and expressly incorporates these other combinations.
The present U.S. Utility Patent Application claims priority pursuant to 35 U.S.C. § 120 as a continuation of U.S. Utility application Ser. No. 17/814,117, entitled “MILLIMETER WAVE RADIO CALIBRATION CIRCUIT”, filed Jul. 21, 2022, which claims priority pursuant to 35 U.S.C. § 119(e) to U.S. Provisional Application No. 63/203,396, entitled “MILLIMETER WAVE RADIO TEST CIRCUIT”, filed Jul. 21, 2021, each of which are hereby incorporated herein by reference in their entirety and made part of the present U.S. Utility Patent Application for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 63203396 | Jul 2021 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17814117 | Jul 2022 | US |
| Child | 18613748 | US |
