Claims
- 1. A method for transmitting data comprising the steps of:
partitioning a string of binary value data into groups of n bits; n being an odd integer; converting each group of n bits into a corresponding group of n+a bits, wherein each group of n+a bits is selected from 2n+a patterns and each of the selected 2n+a patterns does not have bits placed in the same position of the pattern as bits used for framing; and transmitting on a communications channel the selected 2n+a patterns.
- 2. A method for sending data on a communications channel comprising the acts of:
(a) partitioning the data into groups of n-bits; (b) identifying a first bit pattern that delimits units of information on said communications channel; (c) converting each group of n-bits into corresponding groups of n+a bits, selected from 2(n+a) bit patterns wherein none of the corresponding n+a bits include the first bit pattern; and (d) transmitting selected ones of the corresponding n+a bits onto the communications channel.
- 3. The method of claim 2 wherein n=3.
- 4. The method of claim 3 wherein a=1.
- 5. The method of claim 4 further including the act of transmitting a clocking signal to be used to recover said data from the communications channel.
- 6. The method of claim 5 wherein adjacent pairs of clock pulses in said clocking signal are used to send the corresponding n+a bits.
- 7. The method set forth in claim 6 wherein each clock pulse in the pair of adjoining clock pulses gates (n+a)/2 bits into the communications channel.
- 8. The method of claim 7 further including the acts of receiving from the communications channel groups of (n+a) bits;
converting each group of n+a bits into a group of n bits; and converting the group of n bits into a digital data stream.
- 9. A system including:
a source device; a sink device; a data transmission channel operatively coupling the sink device to the source device; a first status transmission channel operatively coupling the source device to the sink device; and an encoder that converts 3 bits into 4 bits that are used to transmit status information on the status transmission channel from the source device to the sink device.
- 10. The system of claim 9 further including a binary register that receives a binary bit string operatively coupled to the encoder.
- 11. The system of claim 10 further including a clock channel that transmits clock signals to gate bits on the status channel.
- 12. The system of claim 11 wherein adjacent pairs of clock pulses on said clock channel gates the 4-bits on the status channel.
- 13. The system of claim 12 wherein each clock pulse in the adjacent pairs of clock pulses gates a pair of the 4-bits on the status channel.
- 14. The system of claim 10 wherein the encoder includes partitioning logic that partitions the binary bit string into groups of the 3-bit;
pattern generation logic responsive to convert each group of 3-bits into the 4-bits; selection logic that selects pairs of bits in said 4-bits to be transmitted on the status transmission channel; and a control logic operatively coupled to the partitioning logic and the selection logic.
- 15. The system of claim 14 wherein the partitioning logic includes n multiplexors having multiple inputs connected to multiple positions of the binary value position register, a single output; and control signal to select the multiplexors.
- 16. The system of claim 14 wherein the pattern generation logic includes multiple two-ways AND/OR logic gates coupled in parallel to the partitioning logic.
- 17. The system of claim 14 wherein the selection logic includes a first multiplexor and a second multiplexor operatively coupled in parallel to the pattern generation logic; and
a pair of OR gates coupled in parallel to the first multiplexor and second multiplexor.
- 18. The system of claim 9 wherein the source device includes a Network Processor.
- 19. The system of claim 18 wherein the sink device includes a Switch Fabric interposer.
- 20. The system of claim 19 wherein the status transmission channel includes a 2-bit bus.
- 21. The system of claim 9 further including a transmit data bus operatively coupling the source device to the sink device; and
a second status control channel operatively interconnecting the sink device to the source device.
- 22. The system of claim 21 further including a decoder receiving groups of 4-bits that are converted into 3-bits and into a digital string.
- 23. The system of claim 22 wherein the decoder includes control logic that generates clocks;
4-bits logic generation circuit operatively coupled to the second status bus and responsive to clock signal from said control logic to generate groups of 4-bits; and 3-bit logic generation circuit responsive to groups of 4-bits to generate 3-bits therefrom.
- 24. The system of claim 23 further including a register operatively coupled to the 3-bit logic generation circuit; and
clock signal from said control logic driving said register to output a digital bit string.
- 25. A method comprising the acts of:
(a) partitioning a binary number into groups of 3-bits; (b) encoding each group of 3-bits into corresponding 4-bits; and (c) transmitting selected ones of the 4-bits with a pair of the 4 bits being transmitted during a first clock cycle followed by another pair of said 4 bits during a second clock cycle.
- 26. The method of claim 25 wherein each group of the 3-bits is selected from a set including 000, 001, 010, 011, 100, 1001, 110 and 111.
- 27. The method of claim 25 wherein each corresponding group of 4-bits is selected from a set including 0000, 0001, 0010, 0100, 0101, 0110, 1000 and 1001.
- 28. The method of claim 25 further including the acts of repeating (b) and (c) until all the groups of 3-bits of the partitioned binary number are transmitted.
CROSS REFERENCE TO RELATED PATENT APPLICATIONS
[0001] The present application claims priority of the U.S. Provisional Application serial No. 60/276,739, filed Mar. 16, 2001.
[0002] Patent application Ser. No. ______ (RPS920020056US1) entitled “Scalable Interface and Method of Transmitting Data Thereon”, assigned to the assignee of the present invention describes a scalable interface using the 2-bit channel and 3b/4b coding.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60276739 |
Mar 2001 |
US |