In data communication devices such as network switches, routers, network processors or network interface cards, it is customary to store the payloads of incoming and/or outbound data packets in a shared packet memory. The packet memory may be partitioned into a rather large number of relatively small storage locations each of which may store a relatively small portion of the data for a packet.
To aid in managing the packet memory, a separate link memory may be provided. The link memory may store linked lists of pointers to packet memory storage locations in which the data for the packet is stored. The link memory may also store a linked list that indicates which storage locations in the packet memory are “free” (i.e., not currently allocated to storing packet data, and therefore available to satisfy a memory allocation request).
It is a frequently an objective of a data communication device that bandwidth be maximized. Accordingly, the number of memory allocation requests that may be handled per clock cycle should be maximized.
The router 10 may include a number of bi-directional ports 12 (i.e., ports that may be used to handle both incoming and outbound packets). In other embodiments, the router 10 may include both ports that are dedicated to receiving incoming packets and ports that are dedicated to transmitting outbound packets.
The router 10 may also include a media access control (MAC) unit 14 which is coupled to the ports 12. The MAC unit 14 may control operation of the ports 12 in accordance with conventional principles.
The router 10 may further include a packet memory management unit 16 provided according to some embodiments. The packet memory management unit 16 may be coupled to the MAC unit 14 and may manage storage of packet data in a packet memory and retrieval of packet data from the packet memory. In some embodiments, the packet memory may be provided off-chip (as indicated in phantom at 18) and may be coupled to the packet memory management unit 16. In other embodiments the packet memory may be on-chip and may be integrated with the packet memory management unit.
The router 10 may also include a control unit 20 which generally controls operation of the router 10 and which is coupled to the MAC unit 14 and to the packet memory management unit 16. In addition, the router 10 may include other customary components, which are not shown.
As seen from
The packet memory management unit 16 also includes a receive controller 24 and a transmit controller 26, both of which are coupled to the memory controller 22. The receive controller 24 may operate in accordance with conventional principles to receive packet data (e.g., from the ports 12 (
The packet memory management unit 16 also includes a link memory 28 which is coupled to the memory controller 22. The link memory 28 stores link pointers used by the memory controller to control memory access operations with respect to the packet memory 18. Details of how the link memory 28 may be operated in accordance with some embodiments will be described below. In some embodiments, the link memory 28 is a dual port memory that allows simultaneously reading out of data from two storage locations in the link memory 28.
The memory controller 22 may include components such as a request arbiter 30, a packet memory controller 32 and a link memory controller 34. The request arbiter 30 may arbitrate among packet data storage/memory allocation requests and packet data retrieval/link-freeing requests received by the memory controller 22. The packet memory controller 32 may be coupled to the packet memory 18 and may handle packet data storage requests and packet data retrieval requests on the basis of pointers stored in the link memory 28. The link memory controller 34 may be coupled to the link memory 28 and may manage storage of pointers (hereinafter referred to as “link pointers”) in storage locations in the link memory 28. The link memory controller 34 may also manage pointers (hereinafter referred to as “list pointers”) that indicate the heads and tails of link lists maintained in the link memory 28. As will be seen, the link lists come in two varieties, namely packet link lists and free link lists. Both types of link lists are structured as linked lists of link pointers stored in storage locations of the link memory 28.
In some embodiments, two or more free link lists may be maintained in the link memory 28. Each of the two free link lists is for indicating a respective linked set of free (not currently allocated) storage locations in the packet memory 18, with the linked nature of each linked set of free links being a product of pointing relationships within the corresponding free link list. In some embodiments, either one of the free link lists is permitted, from time to time, to point to any storage location in the packet memory 18 (provided of course that a free link list may not at a particular time point to a link that is currently pointed to by another link list). In other words, the packet memory is not partitioned between the free link lists, but rather can be freely shared between the two free link lists. With two free link lists being maintained in the link memory 28, and assuming that the link memory 28 is a dual port memory, the memory controller 22 (and hence the packet memory management unit 16) may be able to consistently handle two memory allocation requests in each clock cycle, if required, without pre-fetching locations of free links.
In the example configuration shown in
Because of the pointing of each link pointer stored in a storage location 40 to the next storage location 40 in the same free link list, each free link list takes the form of a linked list, which also indicates a corresponding linked set of storage locations in the packet memory 18. In the example configuration shown in
In the example configuration shown in
In the example configuration shown in
The two packet link lists depicted in
Head and tail information for the packet link list may be stored or calculated by the control unit 20.
As indicated at 100 in
As indicated at 104, the memory controller 22 may perform a process stage for handling packet storage and/or retrieval requests at each clock cycle during operation of the router 10. In a packet memory 18 databus configuration that supports more than one memory allocation request, with a dual port link memory 28 and two free link lists, there are six possible cases for handling in a given clock cycle: (1) handling two memory allocation (packet storage) requests; (2) handling two requests to free memory (packet retrieval requests); (3) handling one memory allocation request and one request to free memory; (4) handling one memory allocation request; (5) handling one request to free memory; and (6) no request to be handled. If the link memory cannot support direct use of its data outputs and inputs and these must be stored, then more (e.g. a plurality) of free link lists can be added depending on how many cycles it takes to get valid data out from the link memory and how many cycles it take to write valid data into the memory and how many ports the link memory has.
At 106 it is determined whether two memory allocation requests are to be serviced in the current clock cycle. If so (case (1)), then as indicated at 108, one of the two requests is serviced by allocating free links in the packet memory 18 pointed to by free link list A, and the other request is serviced by allocating free links in the packet memory 18 pointed to by free link list B. In some embodiments, each of the memory allocations may be made by reference to the head of the respective free link list.
At 110 it is determined whether two requests to free memory are to be serviced in the current clock cycle. If so (case (2)), then as indicated at 112, one of the two requests is serviced by assigning the links freed as a result of the request to free link list A, and the other request is serviced by assigning the links freed as a result of the other request to free link list B. In some embodiments, each assignment of freed links is made to the tail of the respective free link list. In other embodiments, both of the freed sets of links may be assigned to the one of the free link lists that is smaller at the time of the current clock cycle.
At 114 it is determined whether one, and no more than one, memory allocation request is to be serviced in the current clock cycle. If so (case (3) or case (4)), then as indicated at 116, the memory allocation request is serviced by allocating free storage locations in the packet memory 18 pointed to by the one of the free link lists that is larger at the time of the current clock cycle. (The link memory controller keeps a running counter of the number of free links present each cycle in each of the free link lists.)
At 118 it is determined whether one, and no more than one, request to free memory is to be serviced in the current clock cycle. If so (case (3) or case (5)), then as indicated at 120, the request to free memory is serviced by assigning the links freed as a result of the request to the one of the free link lists that is smaller at the time of the current clock cycle.
It will be appreciated that the combined effect of process stages 108 and 116 is that in each clock cycle in which a memory allocation request is serviced, the memory controller 22 allocates links pointed to by one of the free link lists that is at least as large as the other free link list at the time of the clock cycle. (Where two memory allocation requests are serviced in the same clock cycle, the memory controller 22 also allocates links pointed to by the other free link list.) Also, the combined effect of process stages 112 and 120 is that in each clock cycle in which a request to free memory is serviced, the memory controller 22 assigns a freed linked set of storage locations in the packet memory 18 to one of the free link lists that is at least as small as the other free link list at the time of the clock cycle. (Where two requests to free memory are serviced in the same clock cycle, the memory controller 22 may assign the other freed linked set of links to the other free link list.)
In some embodiments, the process illustrated in
In other embodiments, at least a portion of the memory controller 22 may be constituted by a general purpose processor (indicated by reference numeral 140,
By providing a dual port link memory, and maintaining two free link lists in the link memory, a packet memory management unit according to some embodiments may be enabled to consistently provide service for two memory allocation requests per clock cycle, as required, without a need to pre-fetch free link locations. Since pre-fetching is not needed, high bandwidth can be reliably achieved, inasmuch as there is no need to rely on availability of free clock cycles to allow for pre-fetching.
In embodiments described above, two free link lists are maintained in a dual port link memory. The teachings of this disclosure can be extended to maintaining more than two free link lists in a multi-port link memory having more than two ports.
The packet memory management unit embodiments described herein may be applied in data communication devices other than routers. For example, such packet memory management unit embodiments may be included in network switches, network processors and network interface cards.
The several embodiments described herein are solely for the purpose of illustration. The various features described herein need not all be used together, and any one or more of those features may be incorporated in a single embodiment. Therefore, persons skilled in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.