Patent Application
20080122413
The present invention generally relates to semiconductor high voltage generating circuits, and more particularly relates to a method and apparatus for reduced noise high voltage level detection.
Drain pumps and similar high voltage generating circuits are utilized to provide high voltage and/or high current for semiconductor operation. For example, in semiconductor memory devices, drain pumps are used to provide high voltage and high current for programming memory cells. For improved operation of drain pumps, power conservation thereby, efficient operation and other operational control of drain pumps, accurate high voltage detection must be perfomed. Voltage detection circuits, however, require a connection to the high voltage output of the drain pumps with little or no noise thereon. Typically, drain pumps include large capacitors. To conserve power, the drain pumps are turned on and off frequently depending on the output voltage thereof. Because of the capacitors, each time the drain pumps are turned on or turned off, they create noise on the high voltage output thereof. In addition, while the drain pumps are ramping up to a steady state voltage level after being turned on, they also create noise on the power buses. This noise increases as the size of the drain pump increases and is unacceptable for reliable and versatile high voltage detection.
Accordingly, it is desirable to provide a method and apparatus for versatile high voltage detection with immunity to a noisy environment. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.
A method and apparatus is provided for increased noise immunity for a voltage detection circuit by dividing down a high voltage level in response to a current from a current source to generate a level shifted signal and detecting the high voltage level of a high voltage supply signal in response to the level shifted signal.
The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and
The following detailed description of the invention is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description of the invention.
Referring to
The memory cell array 102 includes rewritable non-volatile memory cells that are arranged along word lines and bit lines in a matrix fashion well-known to those skilled in the art. Each of the memory cells is a cell wherein the write function is performed through hot electron injection. In this embodiment, SONOS-type cells may be employed as the non-volatile memory cells. The state machine 104 controls the operation of each circuit in the device in response to each control signal.
In accordance with the present invention, the high-voltage generator 106 generates high voltages that are used within the semiconductor device for memory operations thereof by applying the high voltages to selected cells within the memory cell array 102 via the X-Decoder 114 and the Y-Decoder 120. The high voltages used within the semiconductor memory device include a high voltage for writing data, a high voltage for erasing data, a high voltage for reading data, and a verifying high voltage for checking whether sufficient write/erase has been performed on a subject memory cell at the time of writing or erasing data.
The command register 108 temporarily stores operation commands that are input through the global buffer 112. The address register and decoder 110 temporarily stores input address signals. The I/O buffer and latch circuit 122 controls various signals or data corresponding to I/O terminals. The input/output driver 124 controls the data to be output from the semiconductor memory device 100 and the data to be input thereto.
Referring to
In addition to simple clocks, the clocks 208 may include a clock and one or more clock signal dividers. A plurality of clock signals are generated by a base clock signal from the clock and the base clock signal passing through the one or more clock signal dividers, such as frequency dividers, coupled in series with the clock. One of the plurality of clock signals is chosen by the voltage control signal, acting as a clock selection signal, being provided to a clock signal selector, such as a multiplexer, which receives the plurality of clock signals, the one of the plurality of clock signals selected in response to the clock selection signal. In the embodiment depicted in
V
2
=HV* ((R2+R3)/(R1+R2+R3)) (1)
V
3
=HV* (R3/(R1+R2+R3)) (2)
For a high voltage supply signal having a high voltage level approximately equal to eight volts, such as a high voltage level used for high voltage semiconductor memory operations, and a Vref approximately equal to one volt, to detect voltage differences in the high voltage level within a 500 millivolt (mV) range (e.g., between 7.5 volts and 8.0 volts), the voltage margin detectable in V2 and V3 must necessarily be 62.5 mV as calculated by the equation
Voltage Margin=Target Voltage Difference/(V1/Vref) (3)
where the V1 is the high voltage level HV.
A voltage margin or band gap voltage range must be large enough to reliably detect a change in voltage even in a noisy environment, providing reliable voltage detection decisions. Referring to
I
CS
=Vref/Rref (4)
V
2′=(HV−ICS*R1′)*((R2′+R3′)/(R1′+R2′+R3′)) (5)
V
3′=(HV−ICS* R1′)*(R3′/(R1′+R2′+R3′)) (6)
When the current source 402 is chosen to provide a current such that ICS*R1′ equals four volts (where the high voltage level is eight volts and Vref is one volt), then V1′ is equal to approximately four volts. For a 500 mV detection range at high voltage, using equation (3), the voltage margin is approximately 125 mV. Thus, the present invention increases the voltage margin by one hundred percent providing a versatile high level voltage detector 204 with increased immunity to a noisy environment.
While the current source 402 is depicted as a current reference circuit, the current source could also be a current-steering digital-to-analog converter that changes its current value depending on its mode of operation. For example, at different high voltage levels the current source 402 would provide a different voltage shift.
While at least one exemplary embodiment has been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. For example, instead of a semiconductor memory device, the present invention could be implemented in any semiconductor device utilizing a high voltage detector. In addition, instead of a two level detector, a three or more level detector could be implemented using the present invention. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims and their equivalents.
