Claims
- 1. Apparatus for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed comprising:a two-way compare for comparing first and second state metric input values; a pair of two-way adds in parallel with said two-way compare for respectively adding said first and second state metric input values with a second input value; said second input value being one of a branch metric data dependent term and a branch metric constant term; and said first and second state metric input values of said two-way compare not including said branch metric data dependent term or said branch metric constant term.
- 2. Apparatus for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed comprising:a two-way compare for comparing first and second state metric input values; a pair of two-way adds in parallel with said two-way compare for respectively adding said first and second state metric input values with a second input value; said second input value including a time varying term; and wherein said time varying term is expressed as an output Zn of a partial matched filter or as an output Wn of a matched filter.
- 3. Apparatus for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals as recited in claim 2 includes a maximum of 2L−1 pairs of two-way adds for additions of said time varying terms where a Viterbi detector includes 2L states; where L is a non-zero positive integer value.
- 4. Apparatus for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals in a Viterbi detector including two-way add/compare/select for improved channel speed comprising:a two-way compare for comparing first and second state metric input values; a pair of two-way adds in parallel with said two-way compare for respectively adding said first and second state metric input values with a second input value; said second input value including a constant term; and a maximum of 2L−1 pairs of two-way adds for additions of said constant terms where the Viterbi detector includes 2L states; where L is a non-zero positive integer value.
- 5. Apparatus for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals as recited in claim 2 includes a multiplexer coupled to said pair of two-way adds, said multiplexer receiving a selectable input controlled by said two-way compare.
- 6. Apparatus for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals as recited in claim 2 include a pair of shifts coupled between said pair of two-way adds and said multiplexer, said shifts receiving a shift control input for providing metric bounding to avoid underflow.
- 7. Apparatus for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals as recited in claim 2 wherein said compare includes a hard shift for providing an add for said first state metric input value and then a compare between a resultant first state metric input value and said second state metric input value.
- 8. A two-way add/compare/select for improved channel speed for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals comprising:a two-way compare for comparing first and second state metric input values; a pair of two-way adds in parallel with said two-way compare for respectively adding said first and second state metric input values with a second input value; a multiplexer coupled to said pair of two-way adds, said multiplexer receiving a selectable input controlled by said two-way compare; and a pair of shifts coupled between said pair of two-way adds and said multiplexer, said shifts receiving a shift control input for providing metric bounding to avoid underflow.
- 9. A two-way add/compare/select for improved channel speed for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals as recited in claim 8 wherein said second input value include a time varying term or a constant term.
- 10. A two-way add/compare/select for improved channel speed for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals as recited in claim 9 wherein said time varying term includes an output Zn of a partial matched filter or an output Wn of a matched filter.
- 11. A two-way add/compare/select for improved channel speed for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals as recited in claim 8 wherein said compare includes a hard shift for providing an add for said first state metric input value and then a compare between a resultant first state metric input value and said second state metric input value.
- 12. A two-way add/compare/select for improved channel speed for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals as recited in claim 8 includes a latch coupled to an output of said multiplexer, said latch for holding a resultant state metric value.
CROSS REFERENCE TO RELATED APPLICATION
This application is a continuation-in-part of patent application Ser. No. 09/697,467 filed on Oct. 26, 2000. The above-identified application is incorporated herein by reference.
US Referenced Citations (7)
Number |
Name |
Date |
Kind |
5257272 |
Fredrickson |
Oct 1993 |
A |
5327440 |
Fredrickson et al. |
Jul 1994 |
A |
5430744 |
Fettweis et al. |
Jul 1995 |
A |
5619539 |
Coker et al. |
Apr 1997 |
A |
6097769 |
Sayiner et al. |
Aug 2000 |
A |
6104766 |
Coker et al. |
Aug 2000 |
A |
6212661 |
Rub et al. |
Apr 2001 |
B1 |
Non-Patent Literature Citations (3)
Entry |
T. Conway; Implementation of high speed Viterbi detectors, I.E.E.E. Nov. 25, 1999, vol. 35 No. 24, pp. 20892090.* |
“Reduced-Complexity Viterbi Detector Architectures for Partial Response Signalling” by Fettweis et al., IEEE Globecom 1995 pp. 559-563. |
“Adapative Maximum-Likelihood Receiver for Carrier-Modulated Data-Transmission” by Gottfried Ungerboeck, IEEE Transactions on Communications, May 1974, pp. 624-636. |
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09/697467 |
Oct 2000 |
US |
Child |
09/768802 |
|
US |