Claims
- 1. A method for improving the precision of the laser range detector, comprising the following steps:
emitting a first signal to a target; receiving a second signal which is the first signal reflected by the target; generating one or more delay signals according to the second signal; generating a plurality of pulse clock data from sampling the second signal and the delay signals; calculating a precise time according to the pulse clock data; and calculating a precise distance according to the precise time, wherein the features of the second signal, the delay signals are similar to the first signal.
- 2. The method as claimed in claim 1, wherein each delay signal is delayed by a multiple of a default time from the second signal.
- 3. The method as claimed in claim 1, wherein the pulse clock data are the clock number of the second signal and the delay signals.
- 4. The method as claimed in claim 3, wherein the period of the first signal, the second signal and the delay signals are smaller than the default time.
- 5. An apparatus of a delay circuit for a laser range detector, comprising:
an input terminal for inputting a second signal; one or more delay units for generating one or more delay signals; a switching circuit for selectively outputting one of the second signal or the delay signals; wherein the features of the delay signal is similar to the second signal.
- 6. The apparatus as claimed in claim 5, further comprising one or more TTL units for altering the waveform of the delay signals, wherein each delay unit is corresponded to one TTL unit.
- 7. The apparatus as claimed in claim 5, wherein each delay unit delays the delay signal for a multiple of a default time.
- 8. The apparatus as claimed in claim 5, wherein the period of the second signal and the delay signals are smaller than the default time.
- 9. The apparatus as claimed in claim 5, wherein the Switching Circuit is a N to 1 or gate.
- 10. A laser range detector, comprising:
a processor for calculating a precise time and a precise distance; a clock generator for outputting clock signals; a emitter for emitting a first signal to a target; a receiver for receiving a second signal reflected from a target; a delay circuit for passing the second signal and outputting one or more delay signals; a sampler for sampling the second signal or the delay signals; a register for storing a plurality of pulse clock data corresponding to the second signal or the delay signals; wherein the feature of the second signal and the delay signals are similar to the first signal.
- 11. The apparatus as claimed in claim 10, wherein each delay signal is delayed for a multiple of default time from the second signal.
- 12. The apparatus as claimed in claim 10, wherein the period of the first signal, the second signal and the delay signals are smaller than the default time.
- 13. The apparatus as claimed in claim 10, wherein the processor calculates the precise time and the precise distance according to a plurality of pulse clock data.
- 14. The apparatus as claimed in claim 13, wherein the pulse clock data are the second signal or the delay signals clock parameters.
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation-in-part of U.S. patent application Ser. No. 09/487,623 filed Jan. 20, 2000, which is hereby incorporated by reference.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09487623 |
Jan 2000 |
US |
Child |
10112276 |
Mar 2002 |
US |