Claims
- 1. An apparatus for correcting image read signals comprising:
- a linear sensor for reading an image line by line and outputting read pixel signals of said image and blind pixel signals;
- an A/D converter for converting an output signal of said linear sensor into a digital signal;
- a shift register, coupled to an output of said A/D converter for receiving said digital signal, for storing and outputting a plurality of blind pixel signals of a plurality of lines;
- line memories, coupled to said output of said A/D converter for storing said digital signal;
- a first subtracter for subtracting blind pixel signals from a plurality of preceding lines from blind pixel signals of a current line;
- an adder, having a first input coupled to an output of said first subtracter and a second input for outputting addition data;
- a first latch circuit for latching the addition data from the adder, and having an output coupled to said second input of the adder;
- a second latch circuit for storing the addition data;
- a divider for dividing an output of said second latch circuit so as to obtain an average value;
- a second subtracter for subtracting the average value from an output of at least one of said line memories, and for outputting a corrected signal; and
- a timing generating circuit for controlling said line memories, said shift register and said first and second latch circuits by timing signals.
- 2. An apparatus as claimed in claim 1, wherein said digital signal is 4 bits, the number of said line memories is three and a divisor of said divider is 40.
- 3. An apparatus for correcting image read signals comprising:
- a linear sensor for reading an image line by line and outputting read pixel signals of said image and blind pixel signals;
- an A/D converter for converting an output signal of said linear sensor into a digital signal;
- a shift register, coupled to an output of said A/D converter for receiving said digital signal, for storing and outputting a plurality of blind pixel signals of a plurality of lines;
- line memories, coupled to said output of said A/D converter, for storing said digital signal;
- a first subtracter for subtracting blind pixel signals from a plurality of preceding lines from blind pixels from a current line;
- an adder having a first input coupled to an output of said first subtracter and a second input for outputting addition data;
- a first latch circuit for latching the addition data from the adder, and having an output coupled to said second input of the adder;
- a second latch circuit for storing the addition data and for obtaining an average value by outputting a portion of said stored addition data;
- a second subtracter for subtracting the average value from the output of at least one of said line memories, and for outputting a corrected signal; and
- a timing generating circuit for controlling said line memories, said shift register and said first and second latch circuits by timing signals.
- 4. An apparatus as claimed in claim 3, wherein said digital signal is 4 bits and the number of said line memories is eight.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2-166098 |
Jun 1990 |
JPX |
|
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation-in-part of our prior applicalion Ser. No. 718,468, filed on Jun. 20, 1991, entitled "METHOD OF CORRECTION FOR IMAGE READ SIGNALS" and now abandoned.
US Referenced Citations (4)
Foreign Referenced Citations (1)
Number |
Date |
Country |
53-123617 |
Oct 1978 |
JPX |
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
718468 |
Jun 1991 |
|