Patent Application
20090327564
The inventions generally relate to memory mapping of control and status registers (CSRs).
The coherent system bus (and/or host system bus) in computer systems is typically coupled only to Central Processing Units (CPUs) and not to other classes of devices. However, this has been rapidly changing, and Input/Output (I/O) devices are increasingly being directly coupled to the host system bus (for example, via the CPU socket). Host system buses such as, for example, the Front Side Bus (FSB) and the Quick Path Interconnect bus (QPI, previously known as the Common Serial Interconnect and/or CSI), were designed to couple to CPU type devices and not to I/O devices. In the case of some host system buses such as FSB, fundamental primitives required for coupling I/O devices directly to the host system bus do not exist. In the case of other host system buses such as QPI, coupling I/O devices directly to the host system bus currently require significant hardware. An I/O device that is directly coupled to the host system bus is referred to as a coherent I/O (CIO) device. An I/O device such as a CIO device needs to be able to implement Control and Status Registers (CSRs) which are accessible by other agents that are coupled to the CIO device. In order to implement CSRs, the I/O device needs to “own” a small piece of system memory address space via which CPUs can read/write the CSRs implemented in the I/O device.
The inventions will be understood more fully from the detailed description given below and from the accompanying drawings of some embodiments of the inventions which, however, should not be taken to limit the inventions to the specific embodiments described, but are for explanation and understanding only.
Some embodiments of the inventions relate to memory mapping of control and status registers (CSRs).
In some embodiments control and status registers of a coherent Input/Output device coupled to a host system bus are mapped to a system memory. Direct memory access is provided to the memory mapped control and status registers in the system memory by a CPU that is coupled to the host system bus.
In some embodiments a coherent Input/Output device is coupled to a host system bus. A system memory is to map control and status registers of the coherent Input/Output device, and is to provide direct memory access to the mapped control and status registers.
As discussed above, an I/O device such as a CIO device needs to be able to implement Control and Status Registers (CSRs) which are accessible by other agents connected to the I/O device. In some embodiments, an efficient method of implementing CSRs for a CIO device is performed using only the caching protocol of the CPU(s). This enables an I/O device to be directly coupled to systems of all topologies (for example, in systems using single memory controller architectures such as FSB as well as multiple memory controller architectures such as QPI).
The primary requirement of implementing CSRs is for the I/O device to “own” a small piece of system memory address space via which CPUs can read/write the CSRs implemented in the I/O device. There are difficulties in achieving this for a CIO device. For example, in an FSB type system (for example, with only one MCH) the MCH owns all of the system memory. Thus, a CPU or CIO device does not have the ability to own system memory. Therefore, one CPU cannot directly target accesses to another CPU or CIO device. In this environment, all accesses must happen via system memory or via cache to cache transfers. In a QPI type system (for example, with multiple MCHs) it is possible for the CPU or CIO device to own a part of system memory. However, this is very expensive since a full memory controller must be implemented for the CPU or CIO device. Therefore, according to some embodiments, caching protocols may be used to allow a CIO device to implement CSRs without actually “owning” that address range of system memory.
As illustrated in
At 502 an initialization routine is performed in which the CIO device reads every cacheline BRLD(CSR_BASE), BRLD(CSR_BASE+0x40), BRLD(CSR_BASE+0x80), . . . , BRLD(CSR_BASE+CSR_SIZE) in the CSR write memory region of the system memory. Then the snoopfilter state at the MCH is S@CIO device for all cachelines in the CSR write memory region.
The primary problem with implementing a CSR write mechanism is that the CPU writes to the system memory image, but does not necessarily indicate to the CIO device that a write has occurred. In some embodiments, in order to ensure that the CIO device is aware that a CSR write has occurred is to ensure that a snoop is sent to the CIO device every time the CPU writes a CSR (for example, at 504 in
In some embodiments, a CIO device reads the CSR by reading the image in system memory. The CIO device is not aware of this action as it targets only the system memory image. It is the responsibility of the CIO device to keep the CSR image in system memory up to date by updating the memory image as and when a CSR changes in hardware.
In some embodiments, CSRs are implemented for I/O devices directly coupled to a host system bus (for example, directly coupled to an FSB or a QPI). According to some embodiments, the added burden of building an additional memory controller for the CIO device in the system is not necessary. In some embodiments, a mechanism for updating CSRs may be implemented across all current and future host system interconnects by implementing principles of cache and coherency. In some embodiments, CSRs may be updated in systems using node controllers. In some embodiments, CPU sockets are enabled to be used for coupling high performance I/O devices that make use of coherency. In some embodiments, cache coherent I/O devices may be directly coupled to a coherent system interconnect (for example, such as FSB, QPI, etc.) In some embodiments, a simple implementation may be used for CSRs which takes advantage of access to high performance coherent transactions available only to the CPU. In some embodiments, I/O devices are fully cache coherent and also efficient, thus eliminating the use of low performance transactions such as MMIO (Memory-mapped I/O) transactions.
Although some embodiments have been described herein as being implemented in an FSB and/or QPI environment, according to some embodiments these particular implementations are not required, and embodiments implemented in other architectures may be implemented.
Although some embodiments have been described in reference to particular implementations, other implementations are possible according to some embodiments. Additionally, the arrangement and/or order of circuit elements or other features illustrated in the drawings and/or described herein need not be arranged in the particular way illustrated and described. Many other arrangements are possible according to some embodiments.
In each system shown in a figure, the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar. However, an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein. The various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary.
In the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
An algorithm is here, and generally, considered to be a self-consistent sequence of acts or operations leading to a desired result. These include physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like. It should be understood, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.
Some embodiments may be implemented in one or a combination of hardware, firmware, and software. Some embodiments may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by a computing platform to perform the operations described herein. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, the interfaces that transmit and/or receive signals, etc.), and others.
An embodiment is an implementation or example of the inventions. Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the inventions. The various appearances “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments.
Not all components, features, structures, characteristics, etc. described and illustrated herein need be included in a particular embodiment or embodiments. If the specification states a component, feature, structure, or characteristic “may”, “might”, “can” or “could” be included, for example, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.
Although flow diagrams and/or state diagrams may have been used herein to describe embodiments, the inventions are not limited to those diagrams or to corresponding descriptions herein. For example, flow need not move through each illustrated box or state or in exactly the same order as illustrated and described herein.
The inventions are not restricted to the particular details listed herein. Indeed, those skilled in the art having the benefit of this disclosure will appreciate that many other variations from the foregoing description and drawings may be made within the scope of the present inventions. Accordingly, it is the following claims including any amendments thereto that define the scope of the inventions.
