BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram for explaining widths in a direction of tracks and corresponding combinations of 3 bits based on different levels of multilevel information pits.
FIG. 2 is a diagram for explaining a distribution of the amplitudes of cell-center values.
FIG. 3 is a diagram for explaining positional relationship between preceding and succeeding cells and a light spot in a case where a cell-center value is being sampled.
FIG. 4 is a diagram for explaining positional relationship between preceding and succeeding cells and a light spot in a case where a cell-boundary value is being sampled.
FIG. 5 is a histogram showing results of simulation of the levels of reproduced signals of cell-center values before waveform equalization in a case where 8-ary multilevel data is reproduced.
FIG. 6 is a histogram showing results of simulation of the levels of reproduced signals of cell-boundary values before waveform equalization.
FIG. 7 is a block diagram of an optical disk drive according to a first embodiment of the present invention.
FIGS. 8A and 8B are diagrams showing a binary-to-multilevel converter circuit in the first embodiment.
FIG. 9 is a diagram showing a convolutional encoder in the first embodiment.
FIG. 10 is a table showing bit conversion by a mapping circuit in the first embodiment.
FIG. 11 is a table for converting binary data to 8-ary data by the binary-to-multilevel converter circuit in the first embodiment.
FIG. 12 is a diagram showing sampling points relevant to processing executed by a multilevel-data determining circuit in the first embodiment.
FIG. 13 is a block diagram showing the configuration of the multilevel-data determining circuit in the first embodiment.
FIG. 14 is a diagram showing a cell-center-value-metric calculating circuit and a minimum-cell-center-value-metric selecting circuit in the first embodiment.
FIG. 15 is a table showing an example of reference values used in the cell-center-value-metric calculating circuit.
FIG. 16 is a diagram showing a cell-boundary-value-metric calculating circuit and a minimum-cell-boundary-value-metric selecting circuit in the first embodiment.
FIGS. 17A to 17D show tables showing examples of reference values used in the cell-boundary-value-metric calculating circuit.
FIG. 18 is a diagram showing a branch-metric calculating circuit in the first embodiment.
FIG. 19 is a diagram showing combinations of multilevel values of left and right cells of cell-boundary values.
FIG. 20 is a trellis diagram corresponding to a convolutional encoder in the first embodiment.
FIG. 21 is a diagram showing an example of state transition in the trellis diagram corresponding to the convolutional encoder in the first embodiment.
FIG. 22 is a table showing decoded information and associated branch metrics in the first embodiment.
FIG. 23 is a diagram showing a binary-to-multilevel converter circuit in a second embodiment of the present invention.
FIG. 24 is a diagram showing the relationship between multilevel values of cell-center values and cell-boundary values in the form of a convolutional encoder.
FIG. 25 is a diagram showing sampling points where processing is executed by a multilevel-data determining circuit in the second embodiment.
FIG. 26 is a block diagram showing the configuration of the multilevel-data determining circuit in the second embodiment.
FIG. 27 is a trellis diagram in the second embodiment.
FIG. 28 is a trellis diagram showing results of calculation of branch metrics in the second embodiment.
FIG. 29 is a trellis diagram showing results of calculation of path metrics in the second embodiment.
FIG. 30 is a trellis diagram showing results of calculation of path metrics in the second embodiment.
FIG. 31 is a trellis diagram showing results of calculation of path metrics in the second embodiment.
FIG. 32 is a block diagram showing the configuration of a multilevel-data determining circuit in a third embodiment of the present invention.
FIG. 33 is a trellis diagram of the multilevel-data determining circuit in the third embodiment.
FIG. 34 is a trellis diagram showing results of calculation of path metrics by the multilevel-data determining circuit in the third embodiment.