1. Field of the Invention
The present invention relates to wireless transmission of video information, and in particular, to transmission of uncompressed high definition video information over wireless channels.
2. Description of the Related Technology
With the proliferation of high quality video, an increasing number of electronic devices, such as consumer electronic devices, utilize high definition (HD) video which can require multiple gigabits per second (Gbps) in bandwidth for transmission. As such, when transmitting such HD video between devices, conventional transmission approaches compress the HD video to a fraction of its size to lower the required transmission bandwidth. The compressed video is then decompressed for consumption. However, with each compression and subsequent decompression of the video data, some data can be lost and the picture quality can be reduced.
The High-Definition Multimedia Interface (HDMI) specification allows transfer of uncompressed HD signals between devices via a cable. While consumer electronics makers are beginning to offer HDMI-compatible equipment, there is not yet a suitable wireless (e.g., radio frequency) technology that is capable of transmitting uncompressed HD video signals. Wireless local area network (WLAN) and similar technologies can suffer from interference issues when several devices that do not have reserved bandwidth to carry the uncompressed HD signals are connected to the network. Accordingly a need exists for improved methods and devices of wirelessly transferring uncompressed HD signals.
The system, method, and devices of the invention each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this invention as expressed by the claims which follow, its more prominent features will now be discussed briefly. After considering this discussion, and particularly after reading the section entitled “Detailed Description of Certain Inventive Embodiments” one will understand how the features of this invention provide advantages that may include improved link robustness under poor channel conditions and reduced retransmissions, thereby improving channel efficiency.
One embodiment comprises a method of transmitting uncompressed video. The method includes identifying uncompressed video data for transmitting on a first device at a first transmission rate during at least one reserved time period. The method further includes determining that transmitting the identified uncompressed video data at the first rate would not utilize at least a portion of the reserved time period. The method further includes identifying additional data to transmit during the portion of the reserved time period.
One embodiment comprises a system for transmitting uncompressed video. The system includes a first transmitter configured to transmit uncompressed video data. The system furthers includes at least one processor configured to identify uncompressed video data for transmitting by the first transmitter at a first transmission rate during at least one reserved time period, determine that transmitting the identified uncompressed video data would not utilize at least a portion of the reserved time period, and identify additional data to transmit during the portion of the reserved time period.
One embodiment comprises a system for transmitting uncompressed video. The system includes means for transmitting uncompressed video data and means for processing. The means for processing is configured to identify uncompressed video data for transmitting by the first transmitter at a first transmission rate during at least one reserved time period, determine that transmitting the identified uncompressed video data would not utilize at least a portion of the reserved time period, and identify data to transmit during the portion of the reserved time period.
The following detailed description is directed to certain specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways as defined and covered by the claims. In this description, reference is made to the drawings wherein like parts are designated with like numerals throughout.
Certain embodiments provide a method and system for transmission of uncompressed HD audio and video information from a sender to a receiver over wireless channels. For example, according to one embodiment, a time division multiple access method is used to allocate channel time blocks (CTBs) of a wireless channel to a particular transmitting device. However, the transmitting device may at times encounter a data underflow condition in which insufficient data for filling a CTB is available for transmission. Accordingly, embodiments include systems and methods of using such partially utilized CTBs.
Example implementations of the embodiments in a wireless high definition (HD) audio/video (A/V) system will now be described.
The A/V stations 114 utilize a low-rate (LR) wireless channel 116 (dashed lines in
In one example, the device coordinator 112 is a receiver of video information (hereinafter “receiver 112”), and the station 114 is a sender of the video information (hereinafter “sender 114”). For example, the receiver 112 can be a sink of video and/or audio data implemented, such as, in an HDTV set in a home wireless network environment which is a type of WLAN. The sender 114 can be a source of uncompressed video or audio. Examples of the sender 114 include a set-top box, a DVD player or recorder, digital camera, camcorder, and so forth.
The application layer 210 of the transmitter 202 includes an A/V pre-processing module 211 and an audio video control (AV/C) module 212. The A/V pre-processing module 211 can perform pre-processing of the audio/video such as partitioning of uncompressed video. The AV/C module 212 provides a standard way to exchange A/V capability information. Before a connection begins, the AV/C module negotiates the A/V formats to be used, and when the need for the connection is completed, AV/C commands are used to stop the connection.
In the transmitter 202, the PHY layer 206 includes a low-rate (LR) channel 203 and a high rate (HR) channel 205 that are used to communicate with the MAC layer 208 and with a radio frequency (RF) module 207. In certain embodiments, the MAC layer 208 can include a packetization module (not shown). The PHY/MAC layers of the transmitter 202 add PHY and MAC headers to packets and transmit the packets to the receiver 204 over the wireless channel 201.
In the wireless receiver 204, the PHY/MAC layers 214, 216, process the received packets. The PHY layer 214 includes a RF module 213 connected to the one or more antennas. A LR channel 215 and a HR channel 217 are used to communicate with the MAC layer 216 and with the RF module 213. The application layer 218 of the receiver 204 includes an A/V post-processing module 219 and an AV/C module 220. The module 219 can perform an inverse processing method of the module 211 to regenerate the uncompressed video, for example. The AV/C module 220 operates in a complementary way with the AV/C module 212 of the transmitter 202.
A forward error correction (FEC) subsystem 320 receives output from the scrambler and provides protection against noise, interference and channel fading during wireless data transmission. The FEC subsystem 320 adds redundant data to the scrambled video data input to the subsystem. The redundant data allows the receiver to detect and correct errors without asking the transmitter for additional data. In adding redundant data to the video data, the FEC subsystem 320 can use various error correction codes, such as a Reed-Solomon (RS) encoder and a convolutional code (CC) encoder. In other embodiments, the FEC subsystem 320 may use various other encoders, including, but not limited to, a LDPC encoder, a Hamming encoder, and a Bose, Ray-Chaudhuri, Hocquenghem (BCH) encoder.
The output of the FEC 320 is sent to a bit interleaver 325. The bit interleaver 325 rearranges a sequence of data bits received from the FEC 320. The bit interleaver 325 serves to provide further error-protection over video data transmitted over a wireless medium. The output of the bit interleaver 325 is sent to a mapper 330. The mapper 330 maps data bits to complex (IQ) symbols. The complex symbols are used to modulate a carrier for the wireless transmission described above. The mapper 330 can use various modulation schemes, including, but not limited to, Binary Phase-Shift Keying (BPSK), Quadrature Phase-Shift Keying (QPSK), and Quadrature Amplitude Modulation (QAM). In one embodiment, the mapper 330 is a QAM mapper, for example, a 16-QAM mapper or 64-QAM mapper. QAM is a modulation scheme which conveys data by modulating the amplitude of two carrier waves. The two waves, usually two orthogonal sinusoids, are out of phase with each other by 90° and thus are called quadrature carriers. The number, 16 or 64, in front of “QAM” refers to the total number of symbols to which the mapper can map groups of data bits. For example, a 16-QAM mapper converts 4-bit data into 2̂4=16 symbols. Typically, for QAM mappers, a constellation diagram is used for representing the collection of such symbols.
The output of the mapper 330 is sent to a symbol interleaver 335 that rearranges the sequence of complex symbols output from the mapper. The illustrated symbol interleaver 335 is positioned after the mapper 330. In other embodiments, the symbol interleaver 335 may be positioned between the FEC and the mapper 330 in place of the bit interleaver. In such embodiments, the symbol interleaver permutes the predetermined number of bits as a symbol group. For example, in an embodiment where a QAM mapper maps four data bits to a complex symbol, the symbol interleaver is configured to interleave groups of four data bits.
In an embodiment where the symbol interleaver 335 is positioned after the mapper 330, the symbol interleaver rearranges the sequence of the symbols output from the mapper 330. In one embodiment, the symbol interleaver 335 can include a random interleaver which employs a fixed random permutation order and interleaves symbols according to the permutation order. For example, the random interleaver may use Radix-2 FFT (fast Fourier transform) operation. In other embodiments, the symbol interleaver 335 can include a block interleaver. A block interleaver accepts a set of symbols and rearranges them without repeating or omitting any of the symbols in the set. The number of symbols in each set is fixed for a given interleaver. The interleaver's operation on a set of symbols is independent of its operation on all other sets of symbols.
The output of the symbol interleaver 335 is sent to an inverse Fast Fourier Transform (IFFT) module 340. The IFFT 340 transforms frequency domain data from the error-correcting, mapping and interleaving modules back into corresponding time domain data. The IFFT module 340 converts a number of complex symbols, which represent a signal in the frequency domain, into the equivalent time domain signal. The IFFT module 340 also serves to ensure that carrier signals produced are orthogonal. The output of the IFFT 340 is sent to a cyclic prefix adder 345 so as to decrease receiver complexity. The cyclic prefix adder 345 may also be referred to as a guard interval inserter. The cyclic prefix adder 345 adds a cyclic prefix interval (or guard interval) to an IFFT-processed signal block at its front end. The duration of such a cyclic prefix interval may be 1/32, 1/16, ⅛, or ¼ of the original signal block duration, depending on expected channel conditions and receiver cost and complexity.
At this point of the transmit chain 300, a preamble is part of the header 310 and prior to the IFFT-processed signal block. Generally, a preamble is selected by the designers of the system 200, such as previously described, and is standardized so that all devices of the system understand it. The preamble is used to detect start of the packet, estimate various channel parameters, such as symbol timing, carrier frequency offset.
A symbol shaping module 355 interpolates and low-pass filters the packet signal generated from the IFFT module 340, the cyclic prefix adder 345 and the preamble. The output of the symbol shaping module 355 is a complex baseband of the output signal of the IFFT module 340. An upconverter 360 upconverts the output of the symbol shaping module 355 to a radio frequency (RF) for possible meaningful transmission. A set of transmit antennas 365 transmit the signal output from the upconverter 360 over a wireless medium, such as the wireless channel 201 (
Subsequently to the bit deinterleaving, a FEC decoder 455 decodes the bit stream, thereby removing redundancy added by the FEC 320 of
The control period 504 may be used to allow client devices to transmit control messages to the device coordinator 112. Control messages may include network/device association and disassociation, device discovery, time slot reservations, device capability and preference exchanges, etc. The control period 504 may use a contention based access system such as Aloha, slotted Aloha, CSMA (carrier sensed multiple access), etc., to allow multiple devices to send control messages and to handle collisions of messages from multiple devices. When a message from a client device is received at a device coordinator 112 without suffering a collision, the device coordinator 112 can respond to the request of the message in the beacon period 502 of a subsequent superframe 500. The response may be a time slot reservation of a particular CTB 506 in one or more subsequent superframes 500.
The CTBs 506 are used for transmissions other than beacon messages and contention based control messages which are transmitted in the beacon period 502 and the control period 504. Reserved CTBs 506 are used to transmit commands, isochronous streams and asynchronous data connections. CTB's 506 can be reserved for transmission by a coordinator device to a specific client device, for transmission by a client device to a device coordinator, for transmission by a client device to another client device, etc. A particular CTB 506 can be used to transmit a single data packet or multiple data packets and can include any number of reserved or unreserved CTB's. Unreserved CTB's 508 in the CTB frame 510 can be used for communication of further contention based commands on the low-rate channel such as remote control commands (e.g., CEC commands), MAC control, and management commands.
It is desirable to make the length of the control period 504 as small as possible while still allowing many client devices to be able to successfully access the network without undo time delay, e.g., due to message collision. In one embodiment, the only messages that are sent on a contention basis are control initiation request messages that identify a requesting device and a type of message sequence exchange to be scheduled in a reserved CTB. In this way, the size of the messages that are contention-based are kept to a minimum. All other message exchanges on the low-rate channel can be scheduled.
In the example superframe 500, the superframe 500 period is 20 ms, the control period 504 is 200 Us, the period of each reserved CTB is 667 Is , and the period of the unreserved CTB 508 is 257. However, the period of CTBs may vary from superframe 500 to superframe 500. In additional, in other embodiments different superframe structures may be used. For example, in one embodiment, the control period 504 is 300 μs. The particular example of the superframe 500 of
As further illustrated in
It has been found that the MAC layer 212 (
It is to be recognized that depending on the embodiment, certain acts or events of any of the methods described herein can be performed in a different sequence, may be added, merged, or left out all together (e.g., not all described acts or events are necessary for the practice of the method). Moreover, in certain embodiments, acts or events may be performed concurrently, e.g., through multi-threaded processing, interrupt processing, or multiple processors, rather than sequentially. For example, in one embodiment, the acts and events associated with one or more of the blocks 604 and 606 may not be performed, and the acts and events associated with embodiments of the block 608 are instead performed.
Those of skill will recognize that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
While the above detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the art without departing from the spirit of the invention. As will be recognized, the present invention may be embodied within a form that does not provide all of the features and benefits set forth herein, as some features may be used or practiced separately from others. The scope of the invention is indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.